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HY5V56BLF-I Datasheet

  • HY5V56BLF-I

  • 16Mx16|3.3V|8K|H/8/P/S|SDR SDRAM - 256M

  • 12頁

  • ETC

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HY5V56B(L/S)F-I Series
4 Banks x 4M x 16bits Synchronous DRAM
Preliminary
DESCRIPTION
The HY5V56B(L)F is a 268,435,456bit CMOS Synchronous DRAM, ideally suited for the Mobile applications which
require low power consumption and industrial temperature range. HY5V56B(L)F is organized as 4banks of
4,194,304x16
HY5V56B(L)F is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs
are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high
bandwidth. All input and output voltage levels are compatible with LVTTL.
Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write
cycles initiated by a single control command (Burst length of 1,2,4,8, or full page), and the burst count
sequence(sequential or interleave). A burst of read or write cycles in progress can be terminated by a burst terminate
command or can be interrupted and replaced by a new burst read or write command on any cycle. (This pipelined
design is not restricted by a `2N` rule.)
FEATURES
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Single 3.3鹵0.3V power supply
All device balls are compatible with LVTTL interface
54Ball FBGA (13.5mm x 8.0mm)
All inputs and outputs referenced to positive edge of
system clock
Data mask function by UDQM or LDQM
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Internal four banks operation
Programmable CAS Latency ; 2, 3 Clocks
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Auto refresh and self refresh
8192 refresh cycles / 64ms
Programmable Burst Length and Burst Type
- 1, 2, 4, 8 or Full page for Sequential Burst
- 1, 2, 4 or 8 for Interleave Burst
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ORDERING INFORMATION
Part No.
HY5V56BF-HI
HY5V56BF-8I
HY5V56BF-PI
HY5V56BF-SI
HY5V56B(L)F-HI
HY5V56B(L)F-8I
HY5V56B(L)F-PI
HY5V56B(L)F-SI
Clock Frequency
133MHz
125MHz
100MHz
100MHz
133MHz
125MHz
100MHz
100MHz
Power
Organization
Interface
Package
Normal
4Banks x 4Mbits
x16
Low power
LVTTL
54ball FBGA
This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for
use of circuits described. No patent licenses are implied.
Rev. 0.1/Sep. 02

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