HY57V283220T/ HY5V22F
4 Banks x 1M x 32Bit Synchronous DRAM
DESCRIPTION
The Hynix HY57V283220T / HY5V22F is a 134,217,728-bit CMOS Synchronous DRAM, ideally suited for the memory
applications which require wide data I/O and high bandwidth. HY57V283220T / HY5V22F is organized as 4banks of
1,048,576x32.
HY57V283220T / HY5V22F is offering fully synchronous operation referenced to a positive edge of the clock. All inputs
and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve
very high bandwidth. All input and output voltage levels are compatible with LVTTL.
Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write
cycles initiated by a single control command (Burst length of 1,2,4,8 or full page), and the burst count
sequence(sequential or interleave). A burst of read or write cycles in progress can be terminated by a burst terminate
command or can be interrupted and replaced by a new burst read or write command on any cycle. (This pipelined
design is not restricted by a `2N` rule.)
FEATURES
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
JEDEC standard 3.3V power supply
All device pins are compatible with LVTTL interface
86TSOP-II, 90Ball FBGA with 0.8mm of pin pitch
All inputs and outputs referenced to positive edge of
system clock
Data mask function by DQM0,1,2 and 3
鈥?/div>
鈥?/div>
Internal four banks operation
鈥?/div>
Burst Read Single Write operation
Programmable CAS Latency ; 2, 3 Clocks
鈥?/div>
鈥?/div>
鈥?/div>
Auto refresh and self refresh
4096 refresh cycles / 64ms
Programmable Burst Length and Burst Type
- 1, 2, 4, 8 or full page for Sequential Burst
- 1, 2, 4 or 8 for Interleave Burst
鈥?/div>
ORDERING INFORMATION
Part No.
HY57V283220(L)T-5
HY5V22(L)F-5
HY57V283220(L)T-55
HY5V22(L)F-55
HY57V283220(L)T-6
HY5V22(L)F-6
HY57V283220(L)T-7
HY5V22(L)F-7
HY57V283220(L)T-8
HY5V22(L)F-8
HY57V283220(L)T-P
HY5V22(L)F-P
HY57V283220(L)T-S
HY5V22(L)F-S
Clock Frequency
200MHz
Organization
4Banks x 1Mbits
x32
4Banks x 1Mbits
x32
4Banks x 1Mbits
x32
4Banks x 1Mbits
x32
4Banks x 1Mbits
x32
4Banks x 1Mbits
x32
4Banks x 1Mbits
x32
Interface
LVTTL
Package
86TSOP-II
90Ball FBGA
86TSOP-II
90Ball FBGA
86TSOP-II
90Ball FBGA
86TSOP-II
90Ball FBGA
86TSOP-II
90Ball FBGA
86TSOP-II
90Ball FBGA
86TSOP-II
90Ball FBGA
183MHz
LVTTL
166MHz
LVTTL
143MHz
LVTTL
125MHz
LVTTL
100MHz
LVTTL
100MHz
LVTTL
This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not assume
any responsibility for use of circuits described. No patent licenses are implied.
Rev. 0.5/Oct. 02
HY5V22F相關(guān)型號PDF文件下載
-
型號
版本
描述
廠商
下載
-
英文版
4Mx32|3.3V|4K|55/6/7/8/P/S|SDR SDRAM - 128M
ETC
-
英文版
4Banks x 2M x 32bits Synchronous DRAM
HYNIX [Hyn...
-
英文版
1Mx16|3.3V|4K|H|SDR SDRAM - 16M
ETC
-
英文版
4Mx32|3.3V|4K|7|SDR SDRAM - 128M
ETC
-
英文版
4 Banks x 1M x 32Bit Synchronous DRAM
HYNIX [Hyn...
-
英文版
8Mx16|3.3V|4K|6/K/H/8/P/S|SDR SDRAM - 128M
ETC
-
英文版
4 Banks x 2M x 16bits Synchronous DRAM
HYNIX [Hyn...
-
英文版
8Mx32|3.3V|8K|H/8/P/S|SDR SDRAM - 256M
ETC
-
英文版
16Mx16|3.3V|8K|H|SDR SDRAM - 256M
ETC
-
英文版
32Mx8|3.3V|8K|H/8/P/S|SDR SDRAM - 256M
ETC
-
英文版
2Mx32|3.3V|4K|7|SDR SDRAM - 64M
ETC
-
英文版
4 Banks x 512K x 32Bit Synchronous DRAM
HYNIX [Hyn...
-
英文版
4Mx16|3.3V|4K|H|SDR SDRAM - 64M
ETC
-
英文版
4 Banks x 1M x 16Bit Synchronous DRAM
HYNIX [Hynix Se...
-
英文版
4 Banks x 1M x 32Bit Synchronous DRAM
HYNIX [Hyn...
-
英文版
4 Banks x 1M x 32Bit Synchronous DRAM
HYNIX [Hyn...
-
英文版
4 Banks x 1M x 32Bit Synchronous DRAM
HYNIX [Hyn...
-
英文版
4 Banks x 1M x 32Bit Synchronous DRAM
HYNIX [Hyn...
-
英文版
4 Banks x 1M x 32Bit Synchronous DRAM
HYNIX [Hyn...
-
英文版
4 Banks x 1M x 32Bit Synchronous DRAM
HYNIX [Hyn...
1
2
3
4
5
6
7
8
9
10
11
12
13
14
