The Hynix HY5V16CF is a 16,777,216-bit CMOS Synchronous DRAM, ideally suited for the main memory applications which require
large memory density and high bandwidth. HY5V16CF is organized as 2banks of 524,288x16.
HY5V16CF is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs are synchronized
with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input and output volt-
age levels are compatible with LVTTL.
Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write cycles initiated
by a single control command (Burst length of 1,2,4,8 or Full page), and the burst count sequence(sequential or interleave). A burst of
read or write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a new burst
read or write command on any cycle. (This pipelined design is not restricted by a `2N` rule.)
FEATURES
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Single 3.3鹵0.3V power supply
Note)
All device pins are compatible with LVTTL interface
JEDEC standard 60Ball FD-BGA with 0.65mm of
pin pitch
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Auto refresh and self refresh
4096 refresh cycles / 64ms
Programmable Burst Length and Burst Type
- 1, 2, 4, 8 or Full page for Sequential Burst
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All inputs and outputs referenced to positive edge of
system clock
- 1, 2, 4 or 8 for Interleave Burst
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Programmable CAS Latency ; 2, 3 Clocks
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Data mask function by UDQM or LDQM
Internal four banks operation
ORDERING INFORMATION
Part No.
HY5V16CF-H
HY5V16CF-S
Clock Frequency
133MHz
Power
Organization
2Banks x
512Kbits x16
Interface
Package
10.1x 6.4 60Ball 0.65
Pin -pitch FD-BGA
Normal
100MHz
LVTTL
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any responsibility for use of
circuits described. No patent licenses are implied.
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