HY5DV651622T
4 Banks x 1M x 16Bit DOUBLE DATA RATE SDRAM
DESCRIPTION
The Hynix HY5DV651622 is a 67,108,864-bit CMOS Double Data Rate(DDR) Synchronous DRAM, ideally suited for
the point to point applications which require high bandwidth. HY5DV651622 is organized as 4 banks of 1,048,576x16.
HY5DV651622 offers fully synchronous operations referenced to both rising and falling edges of the clock. While all
addresses and control inputs are latched on the rising edges of the clock(falling edges of the CLK ), Data(DQ), Data
strobes(LDQS/UDQS) and Write data masks(LDM/UDM) inputs are sampled on both rising and falling edges of it. The
data paths are internally pipelined and 2-bit prefetched to achieve very high bandwidth. All input and output voltage
levels are compatible with SSTL_2.
Mode Register Set options include the length of pipeline ( CAS latency of 2 / 3), the number of consecutive read or
write cycles initiated by a single control command (Burst length of 2 / 4 / 8), and the burst count sequence(sequential
or interleave). Because data rate is doubled through reading and writing at both rising and falling edges of the clock,
2X higher data bandwidth can be achieved than that of traditional (single data rate) Synchronous DRAM.
FEATURES
鈥?/div>
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3.3V for V
DD
and 2.5V for V
DDQ
power supply
All inputs and outputs are compatible with SSTL_2
interface
JEDEC standard 400mil 66pin TSOP-II with 0.65mm
pin pitch
Fully differential clock operations(CLK & CLK)
All addresses and control inputs except Data, Data
strobes and Data masks latched on the rising edges
of the clock
Data(DQ) and Write masks(LDM/UDM) latched on
both rising and falling edges of the Data Strobe
Data outputs on LDQS/UDQS edges when read
(edged DQ)
Data inputs on LDQS/UDQS centers when write
鈥?/div>
(centered DQ)
Data strobes synchronized with output data for read
and input data for write
Delay Locked Loop(DLL) installed with DLL reset
mode
Write mask byte controls by LDM and UDM
Programmable CAS Latency 2 / 3 supported
Write Operations with 1 Clock Write Latency
Programmable Burst Length 2 / 4 / 8 with both
sequential and interleave mode
Internal 4 bank operations with single pulsed RAS
Auto refresh and self refresh supported
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ORDERING INFORMATION
Part No.
HY5DV651622TC-G55
HY5DV651622TC-G6
HY5DV651622TC-G7
V
DD
=3.3V
V
DDQ
=2.5V
Power Supply
Clock
Frequency
183MHz
166MHz
143MHz
Organization
Interface
Package
4Banks x 1Mbit x 16
SSTL_2
400mil 66pin
TSOP II
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Rev. 1.1/Apr.01
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