HY5DU564022
4 Banks x 16M x 4Bit Double Data Rate SDRAM
PRELIMINARY
DESCRIPTION
The Hyundai HY5DU564022 is a 268,435,456-bit CMOS Double Data Rate(DDR) Synchronous DRAM, ideally suited
for the main memory applications which require large memory density and high bandwidth. HY5DU564022 is orga-
nized as 4 banks of 16,777,216x4.
HY5DU564022 offers fully synchronous operations referenced to both rising and falling edges of the clock. While all
addresses and control inputs are latched on the rising edges of the clock(falling edges of the CLK), Data(DQ), Data
strobes(LDQS/UDQS) and Write data masks(LDM/UDM) inputs are sampled on both rising and falling edges of it. The
data paths are internally pipelined and 2-bit prefetched to achieve very high bandwidth. All input and output voltage
levels are compatible with SSTL_2.
Mode Register set options include the length of pipeline (CAS latency of 2 / 2.5 / 3), the number of consecutive read or
write cycles initiated by a single control command (Burst length of 2 / 4 / 8), the burst count sequence(sequential or
interleave), DQ FET Control (/QFC) and Output Driver types (Full / Half Strength Driver). Because data rate is doubled
through reading and writing at both rising and falling edges of the clock, 2X higher data bandwidth can be achieved
than that of traditional (single data rate) Synchronous DRAM.
FEATURES
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2.5V V
DD
and V
DDQ
power suppliy
All inputs and outputs are compatible with SSTL_2
interface
JEDEC standard 400mil 66pin TSOP-II with 0.65mm
pin pitch
Fully differential clock operations(CLK & CLK) with
125MHz/133MHz/143MHz
All addresses and control inputs except Data, Data
strobes and Data masks latched on the rising edges
of the clock
Data(DQ) and Write masks(LDM/UDM) latched on
both rising and falling edges of the Data Stobe
Data outputs on LDQS/UDQS edges when read
(edged DQ) Data inputs on LDQS/UDQS centers
when write (centered DQ)
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Delay Locked Loop(DLL) installed with DLL reset
mode
Write mask byte controlled by LDM and UDM
Bytewide data strobes by LDQS and UDQS
Programmable CAS Latency 2 and 2.5 supported
Write Operations with 1 Clock Write Latency
/QFC & Half Strength Driver controlled by EMRS
Programmable Burst Length 2 / 4 / 8 with both
sequential and interleave mode
Internal four bank operations with single pulsed RAS
Auto refresh and self refresh supported
4096 refresh cycles / 64ms
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ORDERING INFORMATION
Part No.
HY5DU564022T-7
HY5DU564022T-75
HY5DU564022T-8
V
DD
=2.5V
V
DDQ
=2.5V
Power Suppy
Clock Frequency
143MHz (*PC266A)
133MHz (*PC266B)
125MHz (*PC200)
Organization
Interface
Package
4Banks
x 16Mbit x 4
SSTL_2
400mil 66pin
TSOP II
* JEDEC Standard compliant
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Rev. 0.1/Jan.00
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