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HY57V651620BLTC-I Datasheet

  • HY57V651620BLTC-I

  • 4Mx16|3.3V|4K|6/7/75/10P/10S|SDR SDRAM - 64M

  • 11頁

  • ETC

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HY57V651620B
4 Banks x 1M x 16Bit Synchronous DRAM
DESCRIPTION
The Hynix HY57V651620B is a 67,108,864-bit CMOS Synchronous DRAM, ideally suited for the Mobile applications
which require low power consumption and extended temperature range. HY57V651620B is organized as 4banks of
1,048,576x16.
HY57V651620B is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and out-
puts are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very
high bandwidth. All input and output voltage levels are compatible with LVTTL.
Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write
cycles initiated by a single control command (Burst length of 1,2,4,8 or Full page), and the burst count
sequence(sequential or interleave). A burst of read or write cycles in progress can be terminated by a burst terminate
command or can be interrupted and replaced by a new burst read or write command on any cycle. (This pipelined
design is not restricted by a `2N` rule.)
FEATURES
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Single 3.3V
鹵
10% power supply
All device pins are compatible with LVTTL interface
JEDEC standard 400mil 54pin TSOP-II with 0.8mm
of pin pitch
All inputs and outputs referenced to positive edge of
system clock
Data mask function by UDQM or LDQM
Internal four banks operation
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Auto refresh and self refresh
4096 refresh cycles / 64ms
Programmable Burst Length and Burst Type
- 1, 2, 4, 8 or Full page for Sequential Burst
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- 1, 2, 4 or 8 for Interleave Burst
Programmable CAS Latency ; 2, 3 Clocks
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ORDERING INFORMATION
Part No.
HY57V651620BTC-6I
HY57V651620BTC-7I
HY57V651620BTC-75I
HY57V651620BTC-10PI
HY57V651620BTC-10SI
HY57V651620BLTC-6I
HY57V651620BLTC-7I
HY57V651620BLTC-75I
HY57V651620BLTC-10PI
HY57V651620BLTC-10SI
Clock Frequency
166MHz
143MHz
133MHz
100MHz
100MHz
166MHz
143MHz
133MHz
100MHz
100Mhz
Power
Organization
Interface
Package
Normal
power
4Banks x 1Mbits
x16
Lower
Power
LVTTL
400mil 54pin TSOP II
This document is a general product description and is subject to change without notice. Hynix semiconductor does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Rev. 0.7/Nov. 01

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