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HY57V561620T-10 Datasheet

  • HY57V561620T-10

  • x16 SDRAM

  • 13頁(yè)

  • ETC

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HY57V561620T
4Banks x 4M x 16Bit Synchronous DRAM
DESCRIPTION
The Hyundai HY57V561620 is a 268,435,456bit CMOS Synchronous DRAM, ideally suited for the main memory appli-
cations which require large memory density and high bandwidth. HY57V561620 is organized as 4 banks of
4,194,304x16.
HY57V561620 is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs
are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high
bandwidth. All input and output voltage levels are compatible with LVTTL.
Programmable options include the length of pipeline ( CAS latency of 2 or 3), the number of consecutive read or write
cycles initiated by a single control command (Burst length of 1,2,4,8 or full page), and the burst count
sequence(sequential or interleave). A burst of read or write cycles in progress can be terminated by a burst terminate
command or can be interrupted and replaced by a new burst read or write command on any cycle. (This pipelined
design is not restricted by a `2N` rule.)
FEATURES
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Single 3.3V
鹵
0.3V power supply
All device pins are compatible with LVTTL interface
JEDEC standard 400mil 54pin TSOP-II with 0.8mm
of pin pitch
All inputs and outputs referenced to positive edge of
system clock
Data mask function by UDQM and LDQM
Internal four banks operation
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Auto refresh and self refresh
8192 refresh cycles / 64ms
Programmable Burst Length and Burst Type
- 1, 2, 4, 8 and Full Page for Sequential Burst
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- 1, 2, 4 and 8 for Interleave Burst
Programmable CAS Latency ; 2, 3 Clocks
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ORDERING INFORMATION
Part No.
HY57V561620T-H
HY57V561620T-8
HY57V561620T-S
HY57V561620T-10
Clock Frequency
133MHz
125MHz
Power
Organization
Interface
Package
Normal
100MHz
100MHz
4Banks x 4Mbits
x16
LVTTL
400mil 54pin TSOP II
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Revision 1.5 / May.00

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