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HY51V65400HG Datasheet

  • HY51V65400HG

  • 16Mx4|3.3V|4K|45|FP/EDO DRAM - 64M

  • 94.49KB

  • 11頁(yè)

  • ETC

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HY51V65400HG
16M x 4Bit Fast Page DRAM
PRELIMINARY
DESCRIPTION
This familiy is a 64Mbit dynamic RAM organized 16,777,216 x 4 bit configuration with Fast Page mode
CMOS DRAMs. Fage page mode offers high speed of random access memory within the same row. The
advanced circuit and process allow this device to achieve high performance and low power dissipation.
features are access time(45ns or 50ns) and refresh cycle(4K ref ) and power consumption (Normal or low
power with self refresh).
Advanced CMOS process as well as circuit techniques for wide operating margins allow this device to
achieve high speed access and high reliability
FEATURES
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Fast page mode operation
Read-modify-write capability
Multi-bit parallel test capability
LVTTL(3.3V) compatible inputs and outputs
/RAS only, CAS-before-/RAS, Hidden Refresh
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JEDEC standard pinout
32pin plastic SOJ/TSOP-II(400mil)
Single power supply of 3.3V +/- 10%
Early write or output enable controlled write
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Fast access time and cycle time
Part No
HY51V65400HG-45
HY51V65400HG-5
HY51V65400HG-6
tRAC
45ns
50ns
60ns
tAA
23ns
25ns
30ns
tCAC
12ns
13ns
15ns
tRC
74ns
84ns
104ns
tHPC
17ns
20ns
25ns
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Power dissipation
45ns
Active
Standby
468mW
50ns
432mW
60ns
396mW
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Refresh cycle
Part No
HY51V65400HG
Ref
4K
Normal
64ms
1.8mW(CMOS level Max)
0.72mW (L-version : Max)
ORDERING INFORMATION
Part Number
HY51V65400HGJ-45
HY51V65400HGJ-5
HY51V65400HGJ-6
HY51V65400HGT-45
HY51V65400HGT-5
HY51V65400HGT-6
Access Time
45ns
50ns
60ns
45ns
50ns
60ns
Package
400mil 32pin SOJ
400mil 32pin TSOP-II
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Rev.0.1/Apr.01

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