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HY29F002 Datasheet

  • HY29F002

  • 2M(X8)|5.0V|45|NOR FLASH - 2M

  • 38頁

  • ETC

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HY29F002T
2 Megabit (256K x 8), 5 Volt-only, Flash Memory
KEY FEATURES
n
5 Volt Read, Program, and Erase
鈥?Minimizes system-level power requirements
n
High Performance
鈥?Access times as fast as 45 ns
n
Low Power Consumption
鈥?20 mA typical active read current
鈥?30 mA typical program/erase current
鈥?1 碌A(chǔ) typical CMOS standby current
n
Compatible with JEDEC Standards
鈥?Package, pinout and command-set
compatible with the single-supply Flash
device standard
鈥?Provides superior inadvertent write
protection
n
Sector Erase Architecture
鈥?Boot sector architecture with top boot
block location
鈥?One 16 Kbyte, two 8 Kbyte, one 32 Kbyte
and three 64K byte sectors
鈥?A command can erase any combination of
sectors
鈥?Supports full chip erase
n
Erase Suspend/Resume
鈥?Temporarily suspends a sector erase
operation to allow data to be read from, or
programmed into, any sector not being
erased
GENERAL DESCRIPTION
The HY29F002T is an 2 Megabit, 5 volt-only
CMOS Flash memory organized as 262,144
(256K) bytes. The device is offered in industry-
standard 32-pin TSOP and PLCC packages.
The HY29F002T can be programmed and erased
in-system with a single 5-volt V
CC
supply. Inter-
nally generated and regulated voltages are pro-
vided for program and erase operations, so that
the device does not require a high voltage power
supply to perform those functions. The device can
also be programmed in standard EPROM pro-
grammers. Access times as fast as 55ns over the
full operating voltage range of 5.0 volts 鹵 10% are
offered for timing compatibility with the zero wait
state requirements of high speed microprocessors.
A 45ns version operating over 5.0 volts 鹵 5% is
also available. To eliminate bus contention, the
18
A[17:0]
RESET#
CE#
OE#
WE#
DQ[7:0]
8
n
Sector Protection
鈥?Any combination of sectors may be
locked to prevent program or erase
operations within those sectors
n
Temporary Sector Unprotect
鈥?Allows changes in locked sectors
(requires high voltage on RESET# pin)
n
Internal Erase Algorithm
鈥?Automatically erases a sector, any
combination of sectors, or the entire chip
n
Internal Programming Algorithm
鈥?Automatically programs and verifies data
at a specified address
n
Fast Program and Erase Times
鈥?Byte programming time: 7 碌s typical
鈥?Sector erase time: 1.0 sec typical
鈥?Chip erase time: 7 sec typical
n
Data# Polling and Toggle Status Bits
鈥?Provide software confirmation of
completion of program or erase
operations
n
Minimum 100,000 Program/Erase Cycles
n
Space Efficient Packaging
鈥?Available in industry-standard 32-pin
TSOP and PLCC packages
LOGIC DIAGRAM
Revision 4.1, May 2001

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