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HT48CA3 Datasheet

  • HT48CA3

  • 8-Bit Remote Type MCU

  • 36頁

  • HOLTEK

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HT48CA3
8-Bit Remote Type MCU
Features
路
Operating voltage: 2.2V~3.6V
路
23 bidirectional I/O lines (max.)
路
1 interrupt input shared with an I/O line
路
8-bit programmable timer/event counter with overflow
路
PFD supported
路
HALT function and wake-up feature reduce power
consumption
路
8-level subroutine nesting
路
Up to 1ms instruction cycle with 4MHz system clock at
interrupt and 8-stage prescaler (TMR0)
路
16-bit programmable timer/event counter and
V
DD
=3V
路
Bit manipulation instruction
路
16-bit table read instruction
路
63 powerful instructions
路
All instructions in one or two machine cycles
路
28-pin SKDIP/SOP package
overflow interrupts (TMR1)
路
On-chip crystal and RC oscillator
路
Watchdog Timer
路
24K麓16 program memory ROM
(8K麓16 bits麓3 banks)
路
224麓8 data memory RAM
General Description
The HT48CA3 is an 8-bit high performance, RISC archi-
tecture microcontroller device specifically designed for
multiple I/O control product applications. The data ROM
can be used to store remote control codes. This device
is the mask version which is fully pin and functionally
compatible with the OTP version HT48RA3 device.
The advantages of low power consumption, I/O flexibil-
ity, timer functions, oscillator options, watchdog timer,
programmable frequency divider, HALT and wake-up
functions, as well as low cost, enhance the versatility of
this device to suit a wide range of application possibili-
ties such as industrial control, consumer products, sub-
system controllers, and particularly suitable for use in
products such as universal remote controller (URC).
Block Diagram
T M R 1 C
M
U
X
IN T /P F 0
T M R 1
f
S
Y S
/4
T M R 1
In te rru p t
C ir c u it
P ro g ra m
C o u n te r
B P
S T A C K
IN T C
T M R 0 C
T M R 0
M
U
X
P r e s c a le r
T M R 0
f
S
Y S
P ro g ra m
R O M
E N /D IS
In s tr u c tio n
R e g is te r
M P
M
U
X
W D T S
D A T A
M e m o ry
W D T P r e s c a le r
W D T
M
U
X
W D T O S C
P A 0 ~ P A 7
f
S
Y S
/4
P A C
In s tr u c tio n
D e c o d e r
A L U
T im in g
G e n e ra to r
S h ifte r
P C C
P C
O S C 2
O S C 1
R E S
V D D
V S S
A C C
M U X
P A
P O R T A
P F D
P B C
S T A T U S
P B
P O R T C
P O R T B
P B 0 ~ P B 7
P C 0 ~ P C 5
P F C
P F
P O R T F
P F 0
Rev. 1.40
1
July 16, 2003

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