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HT48C06 Datasheet

  • HT48C06

  • Cost-Effective I/O Type 8-Bit MCU

  • 38頁

  • HOLTEK

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HT48R05A-1/HT48C05/HT48R06A-1/HT48C06
Cost-Effective I/O Type 8-Bit MCU
Features
路
Operating voltage:
路
Buzzer driving pair and PFD supported
路
HALT function and wake-up feature reduce power
f
SYS
=4MHz: 2.2V~5.5V
f
SYS
=8MHz: 3.3V~5.5V
路
13 bidirectional I/O lines
路
An interrupt input shared with an I/O line
路
8-bit programmable timer/event counter with over-
consumption
路
Up to 0.5ms instruction cycle with 8MHz system clock
at V
DD
=5V
路
Allinstructionsinoneortwomachinecycles
路
14-bit table read instruction
路
Two-level subroutine nesting
路
Bit manipulation instruction
路
Powerful instructions:
flow interrupt and 8-stage prescaler
路
On-chip crystal and RC oscillator
路
Watchdog Timer
路
Program memory ROM:
512麓14 for HT48R05A-1/HT48C05
1024麓14 for HT48R06A-1/HT48C06
路
Data memory RAM
62 for HT48R05A-1/HT48C05
63 for HT48R06A-1/HT48C06
路
Low voltage reset function
路
16-pin SSOP package
32麓8 for HT48R05A-1/HT48C05
64麓8 for HT48R06A-1/HT48C06
18-pin DIP/SOP package
General Description
The HT48R05A-1/HT48C05 and HT48R06A-1/
HT48C06 are 8-bit high performance, RISC architec-
ture microcontroller devices specifically designed for
cost-effective multiple I/O control product applications.
The mask version HT48C05 and HT48C06 are fully pin
and functionally compatible with the OTP version
HT48R05A-1 and HT48R06A-1 devices.
The advantages of low power consumption, I/O flexibil-
ity, timer functions, oscillator options, HALT and
wake-up functions, watchdog timer, buzzer driver, as
well as low cost, enhance the versatility of these devices
to suit a wide range of application possibilities such as
industrial control, consumer products, subsystem con-
trollers, etc.
Block Diagram
IN T /P C 0
In te rru p t
C ir c u it
S T A C K 0
P ro g ra m
R O M
P ro g ra m
C o u n te r
S T A C K 1
IN T C
T M R C
T M R
M
U
X
P r e s c a le r
T M R /P C 1
P C 1
f
S
Y S
P C 0
In s tr u c tio n
R e g is te r
M
U
X
M P
D A T A
M e m o ry
W D T S
W D T P r e s c a le r
W D T
M
U
X
f
S
Y S
/4
P C C
In s tr u c tio n
D e c o d e r
A L U
T im in g
G e n e ra to r
S h ifte r
M U X
P C
P O R T C
P C 0 ~ P C 1
B Z /B Z
R C
O S C
S T A T U S
P B C
P B
P O R T B
P B 0 ~ P B 2
P A C
O S C 2
O S
R E
V D
V S
S
C 1
S
D
P O R T A
A C C
P A
P A 0 ~ P A 7
Rev. 1.10
1
June 9, 2004

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