HSP50415EVAL1
TM
Data Sheet
April 2000
File Number
4859
HSP50415EVAL1 Evaluation Kit
The HSP50415EVAL1 is an evaluation kit for the HSP50415
wideband programmable modulator. The kit consists of an
evaluation Circuit Card Assembly (CCA) complete with the
HSP50415 device and additional circuitry to provide for
control via a computer parallel port. Windows based
demonstration software is provided for full user
programmability and control of all HSP50415 operational
modes. The evaluation board provides digital outputs which
are accessible through a standard logic analyzer header. It
also provides both single ended and differential analog
outputs via standard SMA connectors. Documentation
includes a user鈥檚 manual, full evaluation board schematics
and PCB layout materials. Special 鏗乴ter 鏗乴es, pattern 鏗乴es
and example con鏗乬uration script 鏗乴es are included for quickly
con鏗乬uring the board.
Features
鈥?Evaluation CCA Complete With HSP50415 Wideband
Programmable Modulator
鈥?Windows Based Demonstration Software
鈥?Example Files For Common Modulation Techniques
Reference Documents
鈥?HSP50415EVAL1 Demonstration Software in File
HSP50415.exe
鈥?Example Con鏗乬uration Files in *.js, 鏗乴ter 鏗乴es in *.coe, and
Pattern Files in *.pat
鈥?HSP50415EVAL1 Schematics in File sch415bx.pdf
鈥?HSP50415EVAL1 Layout in File fab415bx.pdf
鈥?HSP50415EVAL1 Bill of Material in File bom415bx.pdf
The latest version for all reference materials and programs is
available via the Intersil internet website:
鈥榳ww.intersil.com/commlink/download/hsp50415eval1鈥?
Block Diagram
COMPUTER
PARALLEL
PORT
P1 25 PIN 鈥楧鈥?/div>
LPT PORT
U2
CY37256V CPLD
/4
D3-D6 STATUS
LEDs
U4
HSP50415 WIDEBAND PROG. MOD.
FEMPT, FOVRFL, FFULL LOCKDET
CE, WR, RD, RESET, ADDR<2:0>, INTREQ
CDATA<7:0>
TXEN
ISTRB
DIN<15:0>
I OUT<13:0>
P3 TEST
HEADER
J2
SMA
STATUS /4
CONTROL /8
U1
LVX161284
IEEE XCVR
CONTROL /3
J15 TEST
SOCKET
J13 TEST
SOCKET
U3
ALVCH16823
DATA REG
U7
CY7C1327
SRAM
J14 TEST
SOCKET
/17
U8
HC244
BUFFER
JTAG /6
P5 JTAG
HEADER
IOUTA
DATA /18
CONTROL /7
ADDRESS /20
IOUTB
T1
I OUT
DATACLK
SYSCLK/2
2XSYSCLK
REFCLK
CLK
DEBUG /16
QOUTA
PLLRC
QOUTB
T2
J3
SMA
Q OUT
P2 DEBUG
HEADER
U5
OSC
J5
SMA
U6
OSC
J4
SMA
LOOP
FILTER
EXTERNAL CLK
EXTERNAL CLK
4-1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143
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Intersil and Design is a trademark of Intersil Corporation.
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Copyright
漏
Intersil Corporation 2000
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