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HSP50016JC-75 Datasheet

  • HSP50016JC-75

  • Digital Down Converter

  • 31頁

  • INTERSIL   INTERSIL

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HSP50016
Data Sheet
February 1999
File Number
3288.6
Digital Down Converter
The Digital Down Converter (DDC) is a single chip
synthesizer, quadrature mixer and lowpass 鏗乴ter. Its input
data is a sampled data stream of up to 16 bits in width and
up to a 75 MSPS data rate. The DDC performs down
conversion, narrowband low pass 鏗乴tering and decimation to
produce a baseband signal.
The internal synthesizer can produce a variety of signal
formats. They are: CW, frequency hopped, linear FM up
chirp, and linear FM down chirp. The complex result of the
modulation process is lowpass 鏗乴tered and decimated with
identical real 鏗乴ters in the in-phase (I) and quadrature (Q)
processing chains.
Lowpass 鏗乴tering is accomplished via a High Decimation
Filter (HDF) followed by a 鏗亁ed Finite Impulse Response
(FIR) 鏗乴ter. The combined response of the two stage 鏗乴ter
results in a -3dB to -102dB shape factor of better than 1.5.
The stopband attenuation is greater than 106dB. The
composite passband ripple is less than 0.04dB. The
synthesizer and mixer can be bypassed so that the chip
operates as a single narrow band low pass 鏗乴ter.
The chip receives forty bit serial commands as a control
input. This interface is compatible with the serial I/O port
available on most microprocessors.
The output data can be con鏗乬ured in 鏗亁ed point or single
precision 鏗俹ating point. The 鏗亁ed point formats are 16,
24, 32, or 38-bit, two鈥檚 complement, signed magnitude, or
offset binary.
The circuit provides an IEEE 1149.1 Test Access Port.
Features
鈥?75 MSPS Input Data Rate
鈥?16-Bit Data Input; Offset Binary or 2鈥檚 Complement
Format
鈥?Spurious Free Dynamic Range Through Modulator
>102dB
鈥?Frequency Selectivity: <0.006Hz
鈥?Identical Lowpass Filters for I and Q
鈥?Passband Ripple: <0.04dB
鈥?Stopband Attenuation: >104dB
鈥?Filter -3dB to -102dB Shape Factor: <1.5
鈥?Decimation Factors from 32 to 131,072
鈥?IEEE 1149.1 Test Access Port
鈥?HSP50016-EV Evaluation Board Available
Applications
鈥?Cellular Base Stations
鈥?Smart Antennas
鈥?Channelized Receivers
鈥?Spectrum Analysis
鈥?Related Products: HI5703, HI5746, HI5766 A/Ds
Ordering Information
PART
NUMBER
HSP50016JC-52
HSP50016JC-75
HSP50016GC-52
TEMP. RANGE
(
o
C)
0 to 70
0 to 70
0 to 70
PACKAGE
44 Ld PLCC
44 Ld PLCC
48 Ld CPGA
PKG.
NO.
N44.65
N44.65
G48.A
Block Diagram
16
DATA
CLK
OUTPUT
FORMATTER
OUTPUT
Q
Q
HIGH DECIMATION
FILTER
LOW PASS FIR
FILTER
I
I
HIGH DECIMATION
FILTER
CONTROL
COS
SIN
LOW PASS FIR
FILTER
IQSTRB
CLK
CLK
R
CLK
4R
OR
CLK
2R
IQCLK
COMPLEX
SINUSOID
GENERATOR
TEST ACCESS
PORT/CTRL
TEST ACCESS
PORT
CLK
SER
3-198
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207
|
Copyright
漏
Intersil Corporation 1999

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