音影先锋亚洲天堂网|电影世界尽头的爱完整版播放|国产 熟女 91|高清无码免费观看欧美日韩|韩国一区二区三区黄色录像|美女亚洲加勒比在线|亚洲综合网 开心五月|7x成人在线入口|成人网站免费日韩毛片区|国产黄片?一级?二级?三级

HSP45240JC-33 Datasheet

  • HSP45240JC-33

  • 13頁

  • ETC

掃碼查看芯片數(shù)據(jù)手冊(cè)

上傳產(chǎn)品規(guī)格書

PDF預(yù)覽

TM
HSP45240
Address Sequencer
Description
The Intersil HSP45240 is a high speed Address Sequencer
which provides specialized addressing for functions like
FFTs, 1-D and 2-D filtering, matrix operations, and image
manipulation. The sequencer supports block oriented
addressing of large data sets up to 24-bits at clock speeds
up to 50MHz.
Specialized addressing requirements are met by using the
onboard 24 x 24 crosspoint switch. This feature allows the map-
ping of the 24 address bits at the output of the address genera-
tor to the 24 address outputs of the chip. As a result, bit reverse
addressing, such as that used in FFTs, is made possible.
A single chip solution to read/write addressing is also made
possible by configuring the HSP45240 as two 12-bit
sequencers. To compensate for system pipeline delay, a pro-
grammable delay is provided on 12 of the address outputs.
The HSP45240 is manufactured using an advanced CMOS
process, and is a low power fully static design. The configu-
ration of the device is controlled through a standard micro-
processor interface and all inputs/outputs, with the exception
of clock, are TTL compatible.
September 1997
Features
鈥?Block Oriented 24-Bit Sequencer
鈥?Configurable as Two Independent 12-Bit Sequencers
鈥?24 x 24 Crosspoint Switch
鈥?Programmable Delay on 12 Outputs
鈥?Multi-Chip Synchronization Signals
鈥?Standard
碌P
Interface
鈥?100pF Drive on Outputs
鈥?DC to 50MHz Clock Rate
Applications
鈥?1-D, 2-D Filtering
鈥?Pan/Zoom Addressing
鈥?FFT Processing
鈥?Matrix Math Operations
Ordering Information
PART NUMBER
HSP45240JC-33
HSP45240JC-40
HSP45240JC-50
HSP45240GC-33
HSP45240GC-40
HSP45240GC-50
TEMP.
RANGE (
o
C)
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
PACKAGE
68 Ld PLCC
68 Ld PLCC
68 Ld PLCC
68 Ld PGA
68 Ld PGA
68 Ld PGA
PKG.
NO.
N68.95
N68.95
N68.95
G68.A
G68.A
G68.A
Block Diagram
STARTOUT
ADDVAL
DONE
BLOCKDONE
12
REG
STARTIN
START
CIRCUITRY
SEQUENCE
GENERATOR
24
CROSSPOINT
SWITCH
OUT12-23
OEH
12
DELAY
1-8
OUT0-11
OEL
PROCESSOR INTERFACE
BUSY
DLYBLK
D0-6, CS, A0, WR
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143
|
Intersil (and design) is a trademark of Intersil Americas Inc.
Copyright 漏 Intersil Americas Inc. 2002. All Rights Reserved
1
File Number
2489.3

HSP45240JC-33相關(guān)型號(hào)PDF文件下載

您可能感興趣的PDF文件資料

熱門IC型號(hào)推薦

掃碼下載APP，
一鍵連接廣大的電子世界。

在線人工客服

買家服務(wù)：
賣家服務(wù)：
技術(shù)客服：

0571-85317607

網(wǎng)站技術(shù)支持

13606545031

客服在線時(shí)間周一至周五
9:00-17:30

關(guān)注官方微信號(hào)，
第一時(shí)間獲取資訊。

建議反饋
返回頂部

建議反饋

聯(lián)系人：

聯(lián)系方式：

按住滑塊，拖拽到最右邊
>>
感謝您向阿庫提出的寶貴意見，您的參與是維庫提升服務(wù)的動(dòng)力！意見一經(jīng)采納，將有感恩紅包奉上哦！