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HS9-80C85RH Datasheet

  • HS9-80C85RH

  • Radiation Hardened 8-Bit CMOS Microprocessor

  • 19頁

  • INTERSIL   INTERSIL

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HS-80C85RH
February 1996
Radiation Hardened
8-Bit CMOS Microprocessor
Description
The HS-80C85RH is an 8-bit CMOS microprocessor fabri-
cated using the Intersil radiation hardened self-aligned junc-
tion isolated (SAJI) silicon gate technology. Latch-up free
operation is achieved by the use of epitaxial starting material
to eliminate the parasitic SCR effect seen in conventional
bulk CMOS devices.
The HS-80C85RH is a functional logic emulation of the
HMOS 8085 and its instruction set is 100% software com-
patible with the HMOS device. The HS80C85RH is designed
for operation with a single 5 volt power supply. Its high level
of integration allows the construction of a radiation hardened
microcomputer system with as few as three ICs (HS-
80C85RH CPU, HS83C55RH ROM I/O, and the HS-81C55/
56RH RAM I/O.
Features
鈥?Devices QML Quali鏗乪d in Accordance With
MIL-PRF-38535
鈥?Detailed Electrical and Screening Requirements are
Contained in SMD# 5962-95824 and Intersil鈥?QM Plan
鈥?Radiation Hardened EPI-CMOS
- Parametrics Guaranteed 1 x 10
5
RAD(Si)
- Transient Upset > 1 x 10
8
RAD(Si)/s
- Latch-up Free > 1 x 10
12
RAD(Si)/s
鈥?Low Standby Current 500碌A(chǔ) Max
鈥?Low Operating Current 5.0mA/MHz (X
1
Input)
鈥?Electrically Equivalent to Sandia SA 3000
鈥?100% Software Compatible with INTEL 8085
鈥?Operation from DC to 2MHz, Post Radiation
鈥?Single 5 Volt Power Supply
鈥?On-Chip Clock Generator and System Controller
鈥?Four Vectored Interrupt Inputs
鈥?Completely Static Design
鈥?Self Aligned Junction Isolated (SAJI) Process
鈥?Military Temperature Range -55
o
C to +125
o
C
Pinouts
40 LEAD CERAMIC DUAL-IN-LINE
METAL SEAL PACKAGE (SBDIP)
MIL-STD-1835, CDIP2-T40
TOP VIEW
X1 1
X2 2
RESET OUT 3
SOD 4
SID 5
TRAP 6
RST 7.5 7
RST 6.5 8
RST 5.5 9
INTR 10
INTA 11
AD0 12
AD1 13
AD2 14
AD3 15
AD4 16
AD5 17
AD6 18
AD7 19
GND 20
40 VDD
39 HOLD
38 HLDA
37 CLOCK OUT
36 RESET IN
35 READY
34 IO / M
33 S1
32 RD
31 WR
30 ALE
29 S0
28 A15
27 A14
26 A13
25 A12
24 A11
23 A10
22 A9
21 A8
X1
X2
RESET
OUT
SOD
SID
TRAP
RST 7.5
RST 6.5
RST 5.5
INTR
INTA
AD0
AD1
AD2
AD3
AD4
NC
NC
AD5
AD6
AD7
42 LEAD CERAMIC METAL SEAL
FLATPACK PACKAGE (FLATPACK)
INTERSIL OUTLINE K42.A
TOP VIEW
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
VDD
HOLD
HLDA
CLOCK
OUT
RESET
IN
READY
IO / M
S1
RD
WR
ALE
S0
A15
A14
A13
A12
A11
A10
A9
A8
GND
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207
|
Copyright
漏
Intersil Corporation 1999
Spec Number
File Number
1
518054
3036.2

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