HS-83C55RH Datasheet

IC型號：
HS-83C55RH
PDF描述：
Radiation Hardened 16K Bit CMOS ROM
文件大?。?/label>
698.83KB
PDF頁數(shù)：
12頁
芯片廠家：
INTERSIL

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HS-83C55RH

Radiation Hardened

16K Bit CMOS ROM

ND S

September 1997

ME GN

ter

EC DES H or Cen /tsc

Features

Pinout

OT NEW 5647R pport l.com

OR HS-6 al Su ters

HS-83C55RH 40 LEAD BRAZE SEAL DIP

鈥?Radiation Hardened EPI-CMOS

.in

SE echn www

RAD(Si)

COMPLIANT OUTLINE D5, CONFIGURATION 3

- Total Dose 1 x 10

RAD(Si)/s (Ports and DDR)

TOP VIEW

ou SIL

- Transient Upset > 1 x 10

act TER

- Latch-Up Free > 1 x 10 RAD(Si)/s

nt IN

co 88-

CE1 1

40 VDD

鈥?2048 Words x 8 Bits ROM

1-8

鈥?Electrically Equivalent to Sandia SA3002

鈥?Pin Compatible with Intel 8355

鈥?Bus Compatible with HS-80C85RH

鈥?Single 5 Volt Power Supply

鈥?Low Standby Current 100碌A Max

鈥?Low Operating Current 2mA/MHz

鈥?Completely Static Design

鈥?Internal Address Latches

鈥?Two General Purpose 8-Bit I/O Ports

鈥?Multiplexed Address and Data Bus

鈥?Self Aligned Junction Isolated (SAJI) Process

鈥?Military Temperature Range

-55

C to +125 C

CE2

39 PB7

38 PB6

37 PB5

36 PB4

35 PB3

34 PB2

33 PB1

32 PB0

31 PA7

30 PA6

29 PA5

28 PA4

27 PA3

26 PA2

25 PA1

24 PA0

23 A10

22 A9

21 A8

CLK

RESET

READY

IO/M

IOR

IOW 10

ALE 11

AD0 12

AD1 13

AD2 14

AD3 15

AD4 16

AD5 17

AD6 18

AD7 19

GND 20

Description

The HS-83C55RH is a radiation hardened ROM and I/O chip fabricated

using the Intersil radiation hardened Self-Aligned Junction Isolated

(SAJI) silicon gate technology. Latch-up free operation is achieved by

the use of epitaxial starting material to eliminate the parasitic SCR effect

seen in conventional bulk CMOS devices.

The HS-83C55RH is intended for use with the HS-80C85RH radiation

hardened microprocessor system.

The ROM portion is designed as 16,384 mask programmable cells orga-

nized in a 2048 word x 8-bit format. A maximum post irradiation access

time of 340ns allows the HS-83C55RH to be used with the HS-80C85RH

CPU without any wait states. This ROM is designed for operation utilizing

a single 5 volt power supply.

Block Diagram

CLK

READY

AD0-7

A8-10

CE2

CE1

IO/M

ALE

IOW

RESET

IOR

VDD

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 321-724-7143

Intersil (and design) is a registered trademark of Intersil Americas Inc.

11-1

PORT A

2K X 8

ROM

(8)

PA0-7

PORT B

(8)

PB0-7

File Number

3045.2

型號

版本

描述

廠商

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HS-809
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HS-80A
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HS-80C
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