HS-2420RH
July 1995
Radiation Hardened
Fast Sample and Hold
Description
The HS-2420RH is a radiation hardened monolithic circuit
consisting of a high performance operational ampli鏗乪r with
its output in series with an ultra-low leakage analog switch
and MOSFET input unity gain ampli鏗乪r.
With an external hold capacitor connected to the switch output,
a versatile, high performance sample-and-hold or track-and-
hold circuit is formed. When the switch is closed, the device
behaves as an operation ampli鏗乪r, and any of the standard op
amp feedback networks may be connected around the device
to control gain, frequency response, etc. When the switch is
opened the output will remain at its last level.
Performance as a sample-and-hold compares very favorably
with other monolithic, hybrid, modular, and discrete circuits.
Accuracy to better than 0.01% is achievable over the
temperature range. Fast acquisition is coupled with superior
droop characteristics, even at high temperatures. High slew
rate, wide bandwidth, and low acquisition time produce
excellent dynamic characteristics. The ability to operate at
gains greater than 1 frequently eliminates the need for
external scaling ampli鏗乪rs.
The device may also be used as a versatile operational
ampli鏗乪r with a gated output for applications such as analog
switches, peak holding circuits, etc.
Features
鈥?Maximum Acquisition Time
- 10V Step to 0.1%. . . . . . . . . . . . . . . . . . . . . . . . . . . 4碌s
- 10V Step to 0.01%. . . . . . . . . . . . . . . . . . . . . . . . . . 6碌s
鈥?Maximum Drift Current . . . . . . . . . . . . . . . . . . . . . .10nA
(Maximum Over Temperature)
鈥?TTL Compatible Control Input
鈥?Power Supply Rejection
. . . . . . . . . . . . . . . . . . . . . .鈮?0dB
鈥?Total Gamma Dose. . . . . . . . . . . . . . . . . 1 x 10
5
RAD(SI)
鈥?No Latch-Up
Applications
鈥?Data Acquisition Systems
鈥?D to A Deglitcher
鈥?Auto Zero Systems
鈥?Peak Detector
鈥?Gated Op Amp
Ordering Information
PART NUMBER
HS1-2420RH-Q
TEMPERATURE
RANGE
-55
o
C to +125
o
C
PACKAGE
14 Lead CerDIP
Pinout
14 LEAD CERAMIC DUAL-IN-LINE
FRIT SEAL PACKAGE (CerDIP)
MIL-STD-1835, GDIP1-T14
TOP VIEW
IN- 1
IN+ 2
14 SAMPLE/HOLD
CONTROL
13 GND
12 NC
14 Pin DIP
11 HOLD CAPACITOR
10 NC
9 V+
8 NC
Functional Diagram
OFFSET
ADJUST
3
4
V+
5
-
INPUT
+ INPUT
1
+
2
-
+
-
7
OUTPUT
OFFSET ADJUST 3
OFFSET ADJUST 4
V- 5
NC 6
OUTPUT 7
14
SAMPLE/
HOLD
CONTROL
HS-2420RH
13
5
11
GND V-
HOLD
CAPACITOR
NOTE: Pin Numbers Correspond to DIP Package Only.
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com
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Copyright
漏
Intersil Corporation 1999
Spec Number
File Number
1
518855
3554.1
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