PLL Frequency Synthesizer
Technical Data
HPLL-8001
Features
鈥?Low Operating Current
Consumption (4 mA, typ.)
鈥?High Input Sensitivity, High
Input Frequencies (50 MHz)
鈥?Synchronous Programming of
the Counters (n-, n/a-,
r-counters)
鈥?Switchable Modulus Trigger
Edge
鈥?Large Dividing Ratios for
Small Channel Spacing,
A counter 0 to 127, N counter
3 to 16,380, R counter 3 to
65,535
鈥?Serial Control 3-wire Bus:
Data, Clock (<10 MHz), Enable
鈥?Switchable Polarity and
Programmable Phase Detector
Current
鈥?2 Programmable Outputs
鈥?Digital Phase Detector
Output Signals (e.g. for
External Charge Pump)
鈥?DRFI, DVFI Outputs (e.g. for
Prescaler Standby)
鈥?Lock Detect Output with
Gated Anti-backlash Pulse
(quasi digital lock detect)
Plastic SOP-14
HP
800 LL
YY 1
WW
Description
The HPLL-8001 is a phase-locked
loop (PLL) frequency synthesizer
intended for use in a frequency
generation loop with an external
dual modulus prescaler and VCO.
The VCO frequency is divided by
the dual modulus prescaler, which
is then fed to the internal A and N
counters. The reference frequency
is fed to an internal R counter to
define the channel spacing. Both
frequencies are compared in the
phase detector which drives the
charge pump. A lock detect is
provided to monitor the lock state
of the loop. All blocks are
programmed by a serial 3-wire
bus interface.
Pin Configuration
1
REFI
14
LD
HPLL
8001
YYWW
7
8
VSS
EN
DATA
CLK
VDD
MOD
PO2
PO1
AVDD
PD
AVSS
VCOI
Functional Block Diagram
DATA
CLOCK
ENABLE
Serial
Control Logic
PD
16 bit R
counter
7 bit A
counter
VCOI
14 bit N
counter
Analog
Control
Logic
VDD VSS AVDD AVSS
MOD
DRFI
Phase
PO1
Detector
Modulus
Control
DVFI
Charge
Pump
PO2
Lock
Detect
LD
REFI
Applications
鈥?GSM Handsets and Base
Stations
鈥?PCS/PCN
鈥?DECT
鈥?Wireless LAN