Agilent HPFC-5400 Tachyon DX2
Dual Channel Fibre Channel IC
Product Overview
鈥?4K on chip boot RAM
鈥?Supports fabric, point-to-point
(N_Port) and loop (Public and Private)
topologies
鈥?Optional external boot ROM/Flash
(128K Bytes)
鈥?Eight full-frame inbound buffers and
four full-frame outbound buffers per FC
channel
Product Description
The Tachyon DX2 is a high-
performance PCI/PCI-X native
dual 1 and 2 gigabit/sec Fibre
Channel controller for host bus
adapters and embedded sub-
systems.
DX2 is the fourth member of the
Agilent Technologies family of
Fibre Channel interface control-
lers. It provides the performance
enhancing features of PCI-X and
is a single chip solution that
offers the most economical
component cost savings.
The DX2 interfaces directly to an
industry standard PCI/PCI-X
bus. Each channel can be inde-
pendently configured to use
either an HSPI-compatible 10-bit
external SERDES or to use the
internal SERDES.
Features
鈥?Dual channel Fibre Channel operation
on one chip for the lowest overall FC
solution costs
鈥?Full duplex operation for each channel
鈥?Concurrent for each dual channel
operation at full link rate
鈥?1 and 2 gigabit Fibre Channel operation
support via internal transceivers or
external HSPI-compatible transceivers
(SERDES)
鈥?Dual function industry standard
33/66 MHz PCI or 66/100/133 MHz
PCI-X backplane interface with 32/64
bit support
鈥?3.3V PCI/PCI-X I/O
鈥?Compliance to PCI Local bus Specifica-
tion, Rev 2.2
鈥?MSI (Message Signaled Interrupt)
support
鈥?Compliance to PCI-X Addendum,
Rev 1.0A
鈥?PCI/PCI-X hot plug compatible
鈥?Output impedance control on PCI-X
I/O for point-to-point or multi-point
connectivity
鈥?Eight GPIO pins per channel
鈥?Loss of signal indication (per channel)
during internal serdes mode
鈥?Multiple split read transaction support
on PCI-X
鈥?No external SRAM required for
operation
鈥?State machine processing of inbound
and outbound data
鈥?Fully assisted Class 2 and Class 3 FCP
with simultaneous initiator and target
functionality
鈥?Provision to support auto-speed
negotiation in TSDK software
鈥?Full byte-level parity protection on
internal data path and RAM
鈥?Backwards compatible to Tachyon XL2
programming interface
鈥?Supports ACK_0 and ACK_1 models in
hardware
鈥?Complete sequence segmentation and
reassembly done in hardware
鈥?64-bit addressing (44/45 bits per
Length/Address pair)
鈥?Mechanisms to reduce number of
interrupts generated by the adapter to
help reduce the software overhead
required to support the adapter
鈥?Frame payload size up to 2048 bytes
鈥?Loop map, broadcast, directed reset
and bypass support
鈥?Non-zero login BB_Credit support
鈥?Compliance with FC-AL-2 ANSI
Standard
鈥?Compliance with Hardware Design
Guide for Microsoft Windows NT
Server, Version 2.0
鈥?Compatible with ACPI/Power
Management Specification
鈥?Minimal board space required
Applications
鈥?Embedded subsystems
鈥?Disk arrays
鈥?SCSI bridge
鈥?High performance host bus adapters
AGILENT
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