Tachyon TL
33 MHz PCI to Fibre Channel
Controller
Technical Data
HPFC-5100C
Features
鈥?Second Generation Controller
IC, Based on TACHYON
Family Architecture
鈥?Supports All Fibre Channel
Topologies; Arbitrated Loop
(FC-AL) and N_Port Fabric
Attachment
鈥?Supports Both Class 3 and
Class 2 (via Software)
鈥?33 MHz, 32/64-Bit PCI
Interface
鈥?1 Gigabit/Second Fibre
Channel Rate
鈥?Full Duplex Support with
Parallel Inbound and
Outbound Processing
鈥?32/64-Bit PCI Interface,
Compliant to PCI v2.1
鈥?Complete Hardware Handling
of Entire SCSI I/O via FCP
On-Chip Assists
鈥?Full Initiator and Target
Mode Functionality
assurance of interoperability and
true Fibre Channel performance.
Tachyon TL focuses on mass
storage applications for any
topology that require Class 3 and
2 (via software) and SCSI upper
layer protocol handling. Coupled
with a high performance 33 MHz,
32/64-bit PCI bus interface,
Tachyon TL provides a cost-
effective, high-performance mass
storage solution.
TACHYON Architecture
Tachyon TL continues with the
TACHYON architecture, a
complete hardware-based state
machine design. This architec-
ture does not require an addi-
tional on-board microprocessor
and therefore avoids reduced
performance issues relating to
processor cycles per second and
access time to firmware. Rather,
the TACHYON architecture is
designed to be a single chip Fibre
Channel solution.
Tachyon TL provides the highest
levels of concurrency via
numerous independent functional
blocks providing parallel
processing of data, control, and
commands. In addition, these
blocks process at hardware
speeds versus firmware speeds,
and automate the entire SCSI I/O
in hardware. The result is
minimized latency and I/O over-
head, coupled with the highest
levels of parallelism to provide
maximum I/O rates and
bandwidth.
FC-AL Features
In addition to the high-perfor-
mance architecture, Tachyon TL
offers FC-AL-1 Fibre Channel
features, such as Auto Status,
multiple I/Os in the same loop
arbitration cycle, loop map, loop
broadcast, and loop directed
reset. These features allow the
designer to achieve higher
performance in an arbitrated loop
topology.
Physical Layer
The physical layer interface is the
popular 10-bit wide specification
that allows interfacing to a low-
cost serializer/deserializer
(SerDes) IC. This is the same
physical layer interface that is
popular on Fibre Channel disk
drives today due to its quality
gigabit signaling, small form
factor, and low cost.
Applications
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Motherboard Integration
Host-Based Adapters
Storage Sub-systems
I
2
O Designs
Description
The HPFC-5100C, Tachyon TL, is
a second-generation controller that
leverages extensive experience in
Fibre Channel, established with the
original TACHYON controller.
Tachyon TL carries forward the
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