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HPC Datasheet

  • HPC

  • 361.58KB

  • 30頁

  • ETC

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HPCCOREA High-Performance Microcontroller Core
PRELIMINARY
November 1988
HPCCOREA High-Performance Microcontroller Core
General Description
The HPCCOREA Megacell is the ASIC HPC
TM
Core Mega-
cell available in the cell based design library The HPC core
is the basis for the HPC family of High Performance micro-
controllers available as standard products from National
Semiconductor Each member of the family is built around
this core CPU with a unique memory and I O configuration
to suit specific applications Therefore designers can now
customize the peripherals surrounding the HPC core to
meet their precise needs while integrating additional sys-
tem logic onto the same die A single chip system solution
becomes possible All Cell Based IC鈥檚 are fabricated in Na-
tional鈥檚 advanced 2m dual layer metal microCMOS technol-
ogy This process combined with an advanced architecture
offers fast flexible I O control efficient data manipulation
and high speed computation
The HPC core Megacell permits a complete microcomputer
environment and more on a single chip Customization of
microcontroller applications and inclusion of surrounding
system logic and memory produce a cost effective system
solution for high performance applications Core functions
such as 4 16-bit timers with 3 input capture registers vec-
tored interrupts WATCHDOG
TM
logic and MICROWIRE
PLUS
TM
provide efficient paths for system integration The
ability to address up to 64 kbytes of memory enables the
HPC core to be used in powerful applications typically per-
formed by microprocessors and expensive peripheral chips
The microCMOS process results in very low current drain
and enables the user to select the optimum speed power
product for his system The IDLE and HALT modes provide
further current savings
HPC Core Features
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
16-bit architecture both byte and word
16-bit data bus ALU and registers
64 kbytes of memory mapped addressing
FAST 240 ns for register instructions when using
17 0 MHz clock
High code efficiency most instructions are single byte
16 x 16 multiply and 32 x 16 divide
Eight vectored interrupt sources
Four 16-bit timer counters
Three 16-bit capture registers
WATCHDOG logic
MICROWIRE PLUS serial I O interface
CMOS very low power save modes IDLE and HALT
Programmable wait states
16-bit general purpose address data bus I O port
8-bit general purpose input port
256 byte RAM
Megacell Test Logic
Enhanced access to core features
Block Diagram
HPC Core Megacell
TL U 9982 鈥?1
TRI-STATE is a registered trademark of National Semiconductor Corporation
HPC
TM
MICROWIRE
TM
MICROWIRE PLUS
TM
MOLE
TM
and WATCHDOG
TM
are trademarks of National Semiconductor Corporation
C
1995 National Semiconductor Corporation
TL U 9982
RRD-B30M115 Printed in U S A

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