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HPC-DEV-SYS2-E Datasheet

  • HPC-DEV-SYS2-E

  • High-Performance Communications MicroController

  • 30頁

  • NSC

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HPC36400E HPC46400E High-Performance Communications MicroController
PRELIMINARY
November 1992
HPC36400E HPC46400E
High-Performance Communications MicroController
General Description
The HPC46400E is an upgraded HPC16400 Features have
been added to support V 120 the 8-bit mode has been en-
hanced to support all instructions and the UART has been
changed to provide more flexibility and power The
HPC46400E is fully upward compatible with the HPC16400
The HPC46400E has 4 functional blocks to support a wide
range of communication application-2 HDLC channels 4
channel DMA controller to facilitate data flow for the HDLC
channels programmable serial interface and UART
The serial interface decoder allows the 2 HDLC channels to
be used with devices using interchip serial link for point-to-
point and multipoint data exchanges The decoder gener-
ates enable signals for the HDLC channels allowing multi-
plexed D and B channel data to be accessed
The HDLC channels manage the link by providing sequenc-
ing using the HDLC framing along with error control based
upon a cyclic redundancy check (CRC) Multiple address
recognition modes and both bit and byte modes of opera-
tion are supported
The HPC36400E and HPC46400E are available in 68-pin
PLCC and 80-pin PQFP packages
Y
Y
Y
Y
Y
Features
Y
HPC
TM
family core features
16-bit data bus ALU and registers
64 kbytes of external memory addressing
FAST 20 0 MHz system clock
Four 16-bit timer counters with WATCHDOG
TM
logic
MICROWIRE PLUS
TM
serial I O interface
CMOS low power with two power save modes
Y
Y
Y
Two full duplex HDLC channels
Optimized for ISDN X 25 V 120 and LAPD
applications
Programmable frame address recognition
Up to 4 65 Mbps serial data rate
Built in diagnostics
Synchronous bypass mode
Optional CRC generation
Received CRC bytes can be read by the CPU
Four channel DMA controller
8- or 16-bit external data bus
UART
Full duplex
7 8 or 9 data bits
Even odd mark space or no parity
7 8 1 or 2 stop bit generation
Accurate internal baud rate generation up to 625k
baud without penalty of using expensive crystal
Synchronous and asynchronous modes of operation
Serial Decoder
Supports 6 popular time division multiplexing proto-
cols for inter-chip communications
Optional rate adaptation of 64 kbit s data rate to
56 kbit s
Over
Mbyte of extended addressing
Easy interface to National鈥檚 DASL 鈥楿鈥?and 鈥楽鈥?trans-
ceivers TP3400 TP3410 and TP3420
Commercial (0 C to
a
70 C) and industrial (
b
40 C to
a
85 C)
Block Diagram
TL DD 10422 鈥?1
TapePak and TRI-STATE are registered trademarks of National Semiconductor Corporation
HPC
TM
MICROWIRE PLUS
TM
and WATCHDOG
TM
are trademarks of National Semiconductor Corporation
IBM PC-AT are registered trademarks of International Business Machines Corporation
Sun is a registered trademark of Sun Microsystems
SunOS
TM
is a trademark of Sun Microsystems
UNIX is a registered trademark of AT T Bell Laboratories
C
1995 National Semiconductor Corporation
TL DD10422
RRD-B30M115 Printed in U S A

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