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HMMC-5025 Datasheet

  • HMMC-5025

  • 2 - 50 GHz Distributed Amplifier

  • 7頁

  • AGILENT   AGILENT

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2 鈥?50 GHz Distributed Amplifier
Technical Data
HMMC-5025
Features
鈥?Frequency Range:
2 鈥?50 GHz
鈥?Small Signal Gain:
8.5 dB
鈥?P
-1dB
@ 40 GHz:
12 dBm
鈥?Noise Figure:
< 6 dB @ 2 鈥?35 GHz
< 10 dB @ 35 鈥?50 GHz
鈥?Return Loss:
In/Out: < -10 dB
Description
The HMMC-5025 was designed as
a generic wide band distributed
amplifier, covering the frequency
span 2 鈥?50 GHz. It consists of
seven stages. Each stage is made
up of two cascoded FETs with
gate peripheries of 48 mm per
FET. Both input and output ports
were designed to provide 50 ohm
terminations. Bonding pads are
provided in the layout to allow
amplifier operation at frequencies
lower than 2 GHz by means of
external circuit components.
The HMMC-5025 is typically
biased at V
DD
= 5 volts and
I
DD
= 75 mA. The second gate is
internally biased by means of a
voltage divider network and an
a.c. ground.
Chip Size:
Chip Size Tolerance:
Chip Thickness:
Pad Dimensions:
1720 x 920
碌m
(67.7 x 36.2 mils)
鹵
10
碌m
(鹵 0.4 mils)
127
鹵
15
碌m
(5.0
鹵
0.6 mils)
80 x 80
碌m
(3.2 x 3.2 mils)
Absolute Maximum Ratings
[1]
Symbol
V
DD
I
DD
V
G1
V
G2
P
DC
P
in
T
ch
T
case
T
STG
T
max
Parameters/Conditions
Positive Drain Voltage
Total Drain Current
First Gate Voltage
Second Gate Voltage
DC Power Dissipation
CW Input Power
Operating Channel Temp.
Operating Case Temp.
Storage Temperature
Maximum Assembly Temp.
(for 60 seconds maximum)
Units
V
mA
V
mA
watts
dBm
擄C
擄C
擄C
擄C
-55
-65
+165
+300
-3.5
-3.0
Min.
Max.
7.0
170
0
+3.0
1.2
20
+150
Note:
1. Operation in excess of any one of these conditions may result in permanent
damage to this device. T
A
= 25擄C except for T
ch
, T
STG
, and T
max
.
5965-5446E
6-40

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