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HM62W4100HCLJP-10 Datasheet

  • HM62W4100HCLJP-10

  • 4M High Speed SRAM (1-Mword x 4-bit)

  • 14頁

  • HITACHI

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HM62W4100HC Series
4M High Speed SRAM (1-Mword
脳
4-bit)
ADE-203-1202 (Z)
Preliminary
Rev. 0.0
Sep. 28, 2000
Description
The HM62W4100HC is a 4-Mbit high speed static RAM organized 1-Mword
脳
4-bit. It has realized high
speed access time by employing CMOS process (6-transistor memory cell) and high speed circuit designing
technology. It is most appropriate for the application which requires high speed and high density memory,
such as cache and buffer memory in system. The HM62W4100HC is packaged in 400-mil 32-pin SOJ for
high density surface mounting.
Features
鈥?/div>
Single supply : 3.3 V
鹵
0.3 V
鈥?/div>
Access time : 10 ns (max)
鈥?/div>
Completely static memory
錚?/div>
No clock or timing strobe required
鈥?/div>
Equal access and cycle times
鈥?/div>
Directly TTL compatible
錚?/div>
All inputs and outputs
鈥?/div>
Operating current : 115 mA (max)
鈥?/div>
TTL standby current : 40 mA (max)
鈥?/div>
CMOS standby current : 5 mA (max)
: 1 mA (max) (L-version)
鈥?/div>
Data retension current : 0.6 mA (max) (L-version)
鈥?/div>
Data retension voltage: 2 V (min) (L-version)
鈥?/div>
Center V
CC
and V
SS
type pinout
Preliminary: The specification of this device are subject to change without notice. Please contact your nearest
Hitachi鈥檚 Sales Dept. regarding specification.

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