HM-6561/883
March 1997
256 x 4 CMOS RAM
Description
The HM-6561/883 is a 256 x 4 static CMOS RAM fabricated
using self-aligned silicon gate technology. Synchronous
circuit design techniques are employed to achieve high per-
formance and low power operation.
On-chip latches are provided for address and data outputs
allowing ef鏗乧ient interfacing with microprocessor systems.
The data output buffers can be forced to a high impedance
state for use in expanded memory arrays. The data inputs
and outputs are multiplexed internally for common I/O bus
compatibility.
The HM-6561/883 is a fully static RAM and may be
maintained in any state for an inde鏗乶ite period of time. Data
retention supply voltage and supply current are guaranteed
over temperature.
Features
鈥?This Circuit is Processed in Accordance to MIL-STD-
883 and is Fully Conformant Under the Provisions of
Paragraph 1.2.1.
鈥?Low Power Standby . . . . . . . . . . . . . . . . . . . . 50碌W Max
鈥?Low Power Operation . . . . . . . . . . . . . 20mW/MHz Max
鈥?Fast Access Time. . . . . . . . . . . . . . . . . . . . . . 200ns Max
鈥?Data Retention . . . . . . . . . . . . . . . . . . . . . . . .at 2.0V Min
鈥?TTL Compatible Input/Output
鈥?High Output Drive - 1 TTL Load
鈥?On-Chip Address Registers
鈥?Common Data In/Out
鈥?Three-State Output
鈥?Easy Microprocessor Interfacing
Ordering Information
PACKAGE TEMPERATURE RANGE
CERDIP
-55
o
C to +125
o
C
220ns
HM1-6561B/883
300ns
HM1-6561/883
PKG. NO.
F18.3
Pinout
HM-6561/883 (CERDIP)
TOP VIEW
A3
A2
A1
A0
A5
A6
A7
GND
E
1
2
3
4
5
6
7
8
9
18 VCC
17 A4
16 W
15 S1
14 DQ3
13 DQ2
12 DQ1
11 DQ0
10 S2
PIN
A
E
W
S
DQ
DESCRIPTION
Address Input
Chip Enable
Write Enable
Chip Select
Data In/Out
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207
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Copyright
漏
Intersil Corporation 1999
File Number
2990.1
6-117
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