HM-65262
March 1997
16K x 1 Asynchronous
CMOS Static RAM
Description
The HM-65262 is a CMOS 16384 x 1-bit Static Random
Access Memory manufactured using the Intersil Advanced
SAJI V process. The device utilizes asynchronous circuit
design for fast cycle times and ease of use. The HM-65262
is available in both JEDEC standard 20 pin, 0.300 inch wide
CERDIP and 20 pad CLCC packages, providing high board-
level packing density. Gated inputs lower standby current,
and also eliminate the need for pull-up or pull-down resis-
tors.
The HM-65262, a full CMOS RAM, utilizes an array of six
transistor (6T) memory cells for the most stable and lowest
possible standby supply current over the full military temper-
ature range. In addition to this, the high stability of the 6T
RAM cell provides excellent protection against soft errors
due to noise and alpha particles. This stability also improves
the radiation tolerance of the RAM over that of four transistor
(4T) devices.
Features
鈥?Fast Access Time. . . . . . . . . . . . . . . . . . . . 70/85ns Max
鈥?Low Standby Current. . . . . . . . . . . . . . . . . . . .50碌A(chǔ) Max
鈥?Low Operating Current . . . . . . . . . . . . . . . . . 50mA Max
鈥?Data Retention at 2.0V . . . . . . . . . . . . . . . . . . .20碌A(chǔ) Max
鈥?TTL Compatible Inputs and Outputs
鈥?JEDEC Approved Pinout
鈥?No Clocks or Strobes Required
鈥?Temperature Range . . . . . . . . . . . . . . . +55
o
C to +125
o
C
鈥?Equal Cycle and Access Time
鈥?Single 5V Supply
鈥?Gated Inputs-No Pull-Up or Pull-Down Resistors
Required
Ordering Information
PACKAGE
CERDIP
JAN #
SMD#
CLCC (SMD#)
NOTE:
1. Access Time/Data Retention Supply Current.
TEMP. RANGE
-40
o
C to +85
o
C
-55
o
C to +125
o
C
-55
o
C to +125
o
C
-55
o
C to +125
o
C
70ns/20碌A(chǔ)
(NOTE 1)
85ns/20碌A(chǔ)
(NOTE 1)
HM1-65262B-9
29109BRA
8413203RA
8413203YA
HM1-65262-9
29103BRA
8413201RA
8413201YA
(NOTE 1)
85ns/400碌A(chǔ)
-
-
-
-
PKG. NO.
F20.3
F20.3
F20.3
J20.C
Pinouts
HM-65262 (CERDIP)
TOP VIEW
HM-65262 (CLCC)
TOP VIEW
V
CC
A13
A1
A0
A1
A2
A3
A4
A5
A6
Q
W
1
2
3
4
5
6
7
8
9
20 V
CC
19 A13
18 A12
17 A11
16 A10
15 A9
14 A8
13 A7
12 D
11 E
A2 3
A3 4
A4 5
A5 6
A6 7
Q 8
9 10 11 12
GND
W
E
D
2
A0
1 20 19
18 A12
17 A11
16 A10
15 A9
14 A8
13 A7
A0 - A13
E
Q
D
V
SS
/GND
V
CC
W
Address Input
Chip Enable/Power Down
Data Out
Data In
Ground
Power (+5)
Write Enable
GND 10
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207
|
Copyright
漏
Intersil Corporation 1999
File Number
3002.2
6-1
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