TM
HM-65162
2K x 8 Asynchronous
CMOS Static RAM
Description
The HM-65162 is a CMOS 2048 x 8 Static Random Access
Memory manufactured using the Intersil Advanced SAJI V
process. The device utilizes asynchronous circuit design for
fast cycle time and ease of use. The pinout is the JEDEC 24
pin DIP, and 32 pad 8-bit wide standard which allows easy
memory board layouts flexible to accommodate a variety of
industry standard PROMs, RAMs, ROMs and EPROMs. The
HM-65162 is ideally suited for use in microprocessor based
systems with its 8-bit word length organization. The conve-
nient output enable also simplifies the bus interface by allow-
ing the data outputs to be controlled independent of the chip
enable. Gated inputs lower operating current and also elimi-
nate the need for pull-up or pull-down resistors.
March 1997
Features
鈥?Fast Access Time . . . . . . . . . . . . . . . . . . . 70/90ns Max
鈥?Low Standby Current. . . . . . . . . . . . . . . . . . . . 50碌A(chǔ) Max
鈥?Low Operating Current . . . . . . . . . . . . . . . . . 70mA Max
鈥?Data Retention at 2.0V . . . . . . . . . . . . . . . . . . . 20碌A(chǔ) Max
鈥?TTL Compatible Inputs and Outputs
鈥?JEDEC Approved Pinout (2716, 6116 Type)
鈥?No Clocks or Strobes Required
鈥?Equal Cycle and Access Time
鈥?Single 5V Supply
鈥?Gated Inputs
鈥?No Pull-Up or Pull-Down Resistors Required
Ordering Information
PACKAGE
CERDIP
JAN#
SMD#
CLCC
SMD#
NOTE:
1. Access time/data retention supply current.
TEMP. RANGE
-40
o
C to +85
o
C
-55
o
C to +125
o
C
-55
o
C to +125
o
C
-40
o
C to +85
o
C
-55
o
C to 125
o
C
70ns/20碌A(chǔ)
(NOTE 1)
HM1-65162B-9
29110BJA
8403606JA
HM4-65162B-9
8403606ZA
90ns/40碌A(chǔ)
(NOTE 1)
HM1-65162-9
29104BJA
8403602JA
HM4-65162-9
8403602ZA
8403603JA
HM4-65162C-9
8403603ZA
90ns/300碌A(chǔ)
(NOTE 1)
HM1-65162C-9
-
PKG. NO.
F24.6
F24.6
F24.6
J32.A
J32.A
Pinouts
HM-65162
(CERDIP)
TOP VIEW
NC
A7
HM-65162
(CLCC)
TOP VIEW
V
CC
PIN
NC
NC
30
29 A8
28 A9
27 NC
26 W
25 G
24 A10
23 E
22 DQ7
21 DQ6
DESCRIPTION
No Connect
Address Input
Chip Enable/Power Down
Ground
Data In/Data Out
Power (+5V)
Write Enable
Output Enable
NC
NC
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
1
2
3
4
5
6
7
8
9
24 V
CC
23 A8
22 A9
21 W
20 G
19 A10
18 E
17 DQ7
16 DQ6
15 DQ5
14 DQ4
13 DQ3
A6
A5
A4
A3
A2
5
6
7
8
9
4
3
2
1
32 31
NC
A0 - A10
E
V
SS
/GND
DQ0 - DQ7
V
CC
W
G
A1 10
A0 11
NC 12
DQ0
13
14 15 16
DQ1
DQ2
GND
17
NC
18
DQ3
19
DQ4
20
DQ5
DQ1 10
DQ2 11
GND 12
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143
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Intersil (and design) is a trademark of Intersil Americas Inc.
Copyright 漏 Intersil Americas Inc. 2002. All Rights Reserved
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