Agilent
HDMP-3001
STS-3c/STM-1 Ethernet
over SONET/SDH Mapper
Product Brief
Features
鈥?Single-chip frame processor with
full-duplex mapping of Ethernet
frames into SONET/SDH payload
using the GFP or LAPS protocol
Description
The HDMP-3001 is an integrated
device that provides full-duplex
mapping of Ethernet frames into
an STS-3c SONET/STM-1 SDH
payload as well as complete
SONET/SDH framing. Mapping of
Ethernet frames is performed
using either the LAPS or GFP
protocol.
On the system side, the
HDMP-3001 can be connected to
either an Ethernet PHY or an
Ethernet MAC depending on
system requirements. When
connected to a MAC, it behaves
like any other 100 Mb/s Ethernet
PHY and can be connected to the
same MDIO bus as regular PHY鈥檚.
When connected to a PHY, a
connection to the Ethernet is
achieved with a minimum of
components.
鈥?Integrated SONET STS-3c/SDH
STM-1 framer that terminates and
generates SONET/SDH overhead
limits the number of external
devices required
鈥?System-side Ethernet MII interface
and line-side 8-bit parallel
interface allows for easy hook-up
to standard components
鈥?Availability of both generic
microprocessor interface and
Ethernet MDIO interface provides
for configuration and status
monitoring
鈥?Extensive set of performance
counters
8-bit Generic
Microprocessor Bus
Ethernet
Management Bus
Standard 2-Wire
EEPROM Bus
HDMP-3001 Block Diagram
E1, E2, F1 and DCC
TOH Overhead
Insert
Microprocessor Interface
MDIO Interface
EEPROM Interface
鈥?Configurable by an external
EEPROM (useful in stand-alone
applications)
4 bits at
25 MHz
8 bits at
19.44 MHz to
transceiver
Parallel
Interface
to Line
TX Framer
SPE/VC
Generator
X
43
+1
Scrambler
LAPS/GFP
Frame
Processor
Performance
Monitor
LAPS/GFP
Frame
Processor
TX FIFO
Ethernet
MII
Interface
to
System
鈥?Provides internal loop-back paths
for diagnostics
鈥?Implemented in low-power
0.25 micron CMOS process with
1.8V core and 3.3V I/Os
鈥?160 pin PQFP
TOH Monitor
POH Monitor
8 bits at
19.44 MHz from
transceiver
Rx Framer
Pointer
Processor
X
43
+1
De-scrambler
RX FIFO
4 bits at
25 MHz
TOH Overhead
Extract
GPIO Register
JTAG Test Access Port
E1, E2, F1 and DCC
16 General Purpose Pins
Test Data
1
2
