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HDMP-2689 Datasheet

  • HDMP-2689

  • Quad 2.125/1.0625 GBd Fibre Channel General Purpose SerDes

  • 28頁

  • AGILENT   AGILENT

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Agilent HDMP-2689
Quad 2.125/1.0625 GBd Fibre Channel
General Purpose SerDes
Data Sheet
鈥?Source synchronous single data
rate clocking of transmit parallel
data for 1.0625 GBd serial rate
鈥?MII management interface for chip
control and status
Description
The HDMP-2689 SerDes chip
transmits and receives high
speed serial data over fiber optic
or coaxial cable interfaces that
conform to ANSI X3T11 Fibre
Channel specification. It sup-
ports SerDes-only mode using a
10-bit data interface with op-
tional 8B/10B encoding for fast
backplane applications. The
HDMP-2689 runs at 2.125 GBd or
1.0625 GBd data rates and
provides parallel-to-serial and
serial-to-parallel conversion on
four independent channels
contained in one package. An on-
chip phase locked loop (PLL)
synthesizes the high speed
transmit clock from a low speed
(106.25 MHz) reference. Each
receiver鈥檚 on-chip PLL synchro-
nizes directly to the incoming
data stream, providing clock and
data recovery. Both the transmit-
ter and receiver support differen-
tial I/O for fiber optic component
interfaces, which minimizes
crosstalk and maximizes signal
integrity. Chip control and status
are accessed via the Media
Independent Interface (MII)
defined in IEEE 802.3.
Features
鈥?1.0625GBd and 2.125 GBd serial
data rates
鈥?TX and RX data rates independently
selectable for each channel
鈥?Fibre Channel (T11) compatible
鈥?High speed differential serial I/O
with matched 50鈩?impedance
鈥?Supports Fibre Channel Protocols
FC0
鈥?Dual mode SerDes operation with
10-bit parallel data interface and
optional 8B/10B encode/decode
鈥?Standard comma recognition for
positive (0011111xxx) and negative
(1100000xxx) disparity
鈥?Source-centered, double data rate
clocking of receive parallel data
for 1.0625 GBd and 2.125 GBd
serial rates
鈥?Source synchronous double data
rate clocking of transmit parallel
data for 2.125 GBd serial rate
鈥?1.8V core power supply, 2.5V power
supply for SSTL_2 I/O
鈥?Independent channel power-down
for power savings
鈥?SSTL_2 compliant parallel I/O and
byte clocks
鈥?Low transmit jitter
鈥?Pre-emphasis on serial outputs
controllable via the management
interface
鈥?Loss of signal detection
鈥?AC-coupled differential LVPECL
reference clock input
鈥?Input equalization
鈥?Boundary scan IEEE 1149.1 compliant
鈥?SerDes self-test capability using
PRBS or user-defined patterns
鈥?Local internal loop back of TX
serial data to RX serial data by
channel
鈥?289-pin PBGA
鈥?Testjet compliant

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