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HDMP-1685A Datasheet

  • HDMP-1685A

  • 1.25 Gbps Four Channel SerDes with 5-pin DDR SSTL_2 Parallel...

  • 292.23KB

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Agilent HDMP-1685A
1.25 Gbps Four Channel SerDes
with 5-pin DDR SSTL_2
Parallel Interface
Data Sheet
Features
鈥?5-bit wide Tx, Rx bus pairs
鈥?208-ball, 23 mm TBGA package
鈥?Parallel data I/O and clocks
compatible with SSTL_2
(EIA/JESD8-9)
鈥?125 MHz TC, RC clocks
鈥?One TC clock for 4 channels
鈥?Single or paired RC clocks
鈥?LVTTL RefClk input
鈥?Source synchronous clocking of
transmit data
鈥?Source centered clocking of
receive data
鈥?Double data rate (DDR) parallel
transfers
鈥?Parallel loopback
鈥?Differential BLL serial I/O
鈥?Single +3.3 V power supply
鈥?Copper drive capability
Applications
鈥?High density fast ports
鈥?Fast serial backplanes
鈥?Clusters of computers
鈥?Clusters of network units
鈥?Link aggregation, trunks
The transmitter section鈥檚 PLL
locks to the 125 MHz TC. This
clock is then multiplied by 10 to
generate the 1250 MHz serial
clock for the high-speed serial
outputs. The high-speed outputs
are capable of interfacing directly
to copper cables for electrical
transmission or to a separate fiber
optic module for optical
transmission.
Functional Description
This data sheet describes HDMP-
1685A, a 1.25 Gbps, four-channel,
5-pin per channel parallel interface
SERDES device. The HDMP-1685A
5-pin parallel interface device en-
ables a single ASIC to drive twice as
many channels using half as many
parallel lines. This is accomplished
without increasing the clock
frequency by utilizing the bandwidth
on the parallel interface more
efficiently.
The HDMP-1685A SERDES is a
single silicon bipolar integrated
circuit packaged in a 208-pin BGA.
This integrated circuit provides a
low-cost, small-form-factor physical-
layer solution for multi-link
1.25 Gbps cables or optical trans-
ceivers. Each IC contains transmit
and receive channel circuitry for all
four channels.
A 125 MHz LVTTL reference clock
must be supplied to the reference
clock input pin, RFCT.
The transmitter section accepts
four, 5-bit-wide parallel SSTL_2
data (TX [0:3] [0:4]), a 125 MHz
SSTL_2 byte clock (TC) and seri-
alizes them into four high-speed
serial streams. The parallel data
is expected to be 鈥?B/10B鈥?en-
coded data, or equivalent. TX and
TC are source synchronous. New
data are accepted on both edges
of TC; this is called Double Data
Rate (DDR). HDMP-1685A finds
a sampling window in between
the two edges of TC to latch
TX [0:3] [0:4] data into the input
register of the transmitter section.
This timing scheme assumes that
the driving ASIC and HDMP-1685A
operate in the same clock domain.
8B/10B encoded data comes in
10-bit characters. This data is
latched onto the 5 TX pins of each
channel in 5-bit groups. It is ex-
pected that the beginning half of
each 10-bit character is latched on
the rising edge of TC.

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