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HDMP-1638 Datasheet

  • HDMP-1638

  • Gigabit Ethernet Transceiver Chip with Dual Serial I/O and D...

  • 256.13KB

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Gigabit Ethernet Transceiver Chip
with Dual Serial I/O and
Differential PECL Clock Inputs
Technical Data
HDMP-1638 Transceiver
Features
鈥?IEEE 802.3z Gigabit Ethernet
compatible, Supports
1250 MBd Gigabit Ethernet
鈥?Based on X3T11 鈥?0-Bit
Specification鈥?/div>
鈥?Low Power Consumption
鈥?Transmitter and Receiver
Functions Incorporated
Onto a Single IC
鈥?10 mm, 64-Pin Plastic
Package
鈥?5 Volt Tolerant I/Os
鈥?10-Bit Wide Parallel TTL
Compatible I/Os
鈥?Single +3.3 V Power Supply
鈥?Differential PECL Clock
Inputs
鈥?Dual Serial I/O With
Receive Select
鈥?2kV ESD Protection on
All Pins
Description
The HDMP-1638 transceiver is a
single silicon bipolar integrated
circuit packaged in a plastic QFP
package. It provides a low-cost,
low-power physical layer solution
for 1250 MBd Gigabit Ethernet
or proprietary link interfaces.
It provides complete Serialize/
Deserialize (鈥淪erDes鈥? for copper
transmission, incorporating both
the Gigabit Ethernet transmit and
receive functions into a single
device.
This chip is used to build a high
speed interface (as shown in
Figure 1) while minimizing
board space, power and cost.
It is compatible with the IEEE
802.3z specification.
The transmitter section accepts
10-bit wide parallel TTL data
and serializes this data into two
high speed serial data streams.
The parallel data is expected to
be 鈥?B/10B鈥?encoded data, or
equivalent. This parallel data is
latched into the input register
of the transmitter section on
the rising edge of the 125 MHz
reference clock (used as the
transmit byte clock).
The transmitter section鈥檚 PLL locks
to this user supplied 125 MHz
byte clock. This clock is then
multiplied by 10, to generate the
1250 MHz serial signal clock used
to generate the high speed
outputs. The high speed outputs
are capable of interfacing directly
to copper cables for electrical
transmission or to a separate
fiber optic module for optical
transmission.
The receiver section allows
for the selection of one of two
serial electrical data streams
at 1250 MBd and recovers the
original 10-bit wide parallel data.
The receiver PLL locks onto
the incoming serial signal and
recovers the high speed serial
clock and data. The serial data
is converted back into 10-bit
parallel data, recognizing the
8B/10B comma character to
establish byte alignment.
Applications
鈥?1250 MBd Gigabit Ethernet
Interface
鈥?High Speed Proprietary
Interface
鈥?Backplane Serialization/Bus
Extender
CAUTION: As with all semiconductor IC鈥檚, it is advised that normal static precautions be taken in handling
and assembly of this component to prevent damage and/or degradation which may be induced by
electrostatic discharge (ESD).

HDMP-1638相關(guān)型號PDF文件下載

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  • 英文版
    Optoelectronic
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    Optoelectronic
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    FIBER OPTIC SUPPORT CIRCUIT
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    Quad Port Bypass Circuit for Fibre Channel Arbitrated Loops
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    Quad Port Bypass Circuit for Fibre Channel Arbitrated Loops
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    Quad Port Bypass Circuit for Fibre Channel Arbitrated Loops
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    Quad Port Bypass Circuit with CDR for Fibre Channel Arbitrat...
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    Quad Port Bypass Circuit with CDR for Fibre Channel Arbitrat...
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    Octal Cell Port Bypass Circuit without Clock and Data Recove...
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  • 英文版
    Octal Cell Port Bypass Circuit without Clock and Data Recove...
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    Octal Cell Port Bypass Circuit with CDR and Data Valid Detec...
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    AGILENT HDMP-0552 QUAD PORT BYPASS CIRCUIT WITH CDR AND DATA...
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    AGILENT HDMP-0552 QUAD PORT BYPASS CIRCUIT WITH CDR A...
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  • 英文版
    Receiver
    ETC

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