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HDMP-1546A Datasheet

  • HDMP-1546A

  • IC-TRANSCEIVER

  • 230.59KB

  • 16頁

  • ETC

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Fibre Channel Transceiver Chip
Technical Data
HDMP-1536A Transceiver
HDMP-1546A Transceiver
Features
鈥?ANSI X3.230-1994 Fibre
Channel Compatible (FC-0)
鈥?Supports Full Speed
(1062.5 MBd) Fibre Channel
鈥?Compatible with 鈥淔ibre
Channel 10-Bit Interface鈥?/div>
Specification
鈥?Low Power Consumption,
630 mW
鈥?Transmitter and Receiver
Functions Incorporated onto
a Single IC
鈥?Auto Frequency Lock
鈥?Small Package Profile
HDMP-1536A, 10x10 mm
QFP
HDMP-1546A, 14x14 mm
QFP
鈥?10-Bit Wide Parallel TTL
Compatible I/Os
鈥?Single +3.3 V Power Supply
鈥?5 Volt Tolerant I/Os
鈥?2 kV ESD Protection on All Pins
鈥?High Speed Proprietary
Interface
鈥?High Speed Backplane
Interface
Description
The HDMP-1536/46A transceiver
is a single silicon bipolar
integrated circuit packaged in a
plastic QFP package. It provides
a low-cost, low-power physical
layer solution for 1062.5 MBd
Fibre Channel or proprietary link
interfaces. It provides complete
FC-0 functionality for copper
transmission, incorporating both
the Fibre Channel FC-0 transmit
and receive functions into a
single device.
This chip is used to build a high-
speed interface (as shown in
Figure 1) while minimizing board
space, power, and cost. It is
compatible with both the ANSI
X3.230-1994/AM 1 - 1996
document and the 鈥淔ibre Channel
10-bit Interface鈥?specification.
The transmitter section accepts
10-bit wide parallel TTL data and
multiplexes this data into a high-
speed serial data stream. The
parallel data is expected to be
8B/10B encoded data, or
equivalent. This parallel data is
latched into the input register of
the transmitter section on the
rising edge of the 106.25 MHz
reference clock (used as the
transmit byte clock).
The transmitter section鈥檚 PLL
locks to this user supplied 106.25
MHz byte clock. This clock is
then multiplied by 10, to generate
the 1062.5 MHz serial signal
clock used to generate the high-
speed output. The high-speed
outputs are capable of interfacing
directly to copper cables for
electrical transmission or to a
separate fiber-optic module for
optical transmission.
The receiver section accepts a
serial electrical data stream at
1062.5 MBd and recovers the
original 10-bit wide parallel data.
The receiver PLL locks onto the
incoming serial signal and
Applications
鈥?1062.5 MBd Fibre Channel
Interface
鈥?FC Interface for Disk Drives
and Arrays
鈥?Mass Storage System I/O
Channel
鈥?Work Station/Server I/O
Channel

HDMP-1546A相關型號PDF文件下載

  • 型號
    版本
    描述
    廠商
    下載
  • 英文版
    Optoelectronic
    ETC
  • 英文版
    Optoelectronic
    ETC
  • 英文版
    FIBER OPTIC SUPPORT CIRCUIT
    ETC
  • 英文版
    FIBER OPTIC SUPPORT CIRCUIT
    ETC
  • 英文版
    FIBER OPTIC SUPPORT CIRCUIT
    ETC
  • 英文版
    1.0625-1.25 GBd Single Port Bypass Circuit wirh CDR for Fibr...
    ETC
  • 英文版
    Port Bypass Circuits for Fibre Channel Arbitrated Loop Stand...
    HP [Agilen...
  • 英文版
    Single Port Bypass Circuit with CDR & Data Valid Detection C...
    HP [Agilen...
  • 英文版
    Quad Port Bypass Circuit for Fibre Channel Arbitrated Loops
    AGILENT
  • 英文版
    Quad Port Bypass Circuit for Fibre Channel Arbitrated Loops
    HP [Agilen...
  • 英文版
    Quad Port Bypass Circuit for Fibre Channel Arbitrated Loops
    AGILENT
  • 英文版
    Quad Port Bypass Circuit for Fibre Channel Arbitrated Loops
    HP [Agilen...
  • 英文版
    Quad Port Bypass Circuit with CDR for Fibre Channel Arbitrat...
    AGILENT
  • 英文版
    Quad Port Bypass Circuit with CDR for Fibre Channel Arbitrat...
    HP [Agilen...
  • 英文版
    Octal Cell Port Bypass Circuit without Clock and Data Recove...
    AGILENT
  • 英文版
    Octal Cell Port Bypass Circuit without Clock and Data Recove...
    HP [Agilen...
  • 英文版
    Octal Cell Port Bypass Circuit with CDR and Data Valid Detec...
    HP [Agilen...
  • 英文版
    AGILENT HDMP-0552 QUAD PORT BYPASS CIRCUIT WITH CDR AND DATA...
    ETC
  • 英文版
    AGILENT HDMP-0552 QUAD PORT BYPASS CIRCUIT WITH CDR A...
    ETC [ETC]
  • 英文版
    Receiver
    ETC

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