音影先锋亚洲天堂网|电影世界尽头的爱完整版播放|国产 熟女 91|高清无码免费观看欧美日韩|韩国一区二区三区黄色录像|美女亚洲加勒比在线|亚洲综合网 开心五月|7x成人在线入口|成人网站免费日韩毛片区|国产黄片?一级?二级?三级

HDMP-1514 Datasheet

  • HDMP-1514

  • Fibre Channel Transmitter and Receiver Chipset

  • 26頁(yè)

  • AGILENT   AGILENT

掃碼查看芯片數(shù)據(jù)手冊(cè)

上傳產(chǎn)品規(guī)格書(shū)

PDF預(yù)覽

Fibre Channel Transmitter and
Receiver Chipset
Technical Data
HDMP-1512 Transmitter
HDMP-1514 Receiver
Features
鈥?ANSI X3.230-1994 Fibre
Channel Standard
Compatible (FC-0)
鈥?Selectable 531.25 Mbaud or
1062.5 Mbaud Data Rates
鈥?Selectable On Chip Laser
Driver and 50
鈩?/div>
Cable
Driver
鈥?TTL Compatible I/Os
鈥?Single +5.0 V Power Supply
Applications
鈥?Mass Storage System I/O
Channel
鈥?Work Station/Server I/O
Channel
鈥?High Speed Peripheral
Interface
converts the data to a serial
stream and sends it over a copper
cable or fiber-optic link. The
receiver converts the serial data
stream back to parallel encoded
data and presents it, along with
the recovered transmit byte
clock, to the receiving system.
The sending system has the
option to electrically wrap the
transmitted data back to the local
receiver. It is possible to transmit
over the cable driver, or laser
driver when data is being
wrapped back to the local
receiver.
The two-chip set (transmitter
chip and receiver chip) is
compatible with the FC-0 layer of
the American National Standards
Institute (ANSI), Fibre Channel
specification, X3.230-1994. This
specification defines four
standard rates of operation for
Fibre Channel links. The HDMP-
1512 and HDMP-1514 chip-set
will operate at the two highest
defined serial rates of 531.25
Mbaud and 1062.5 Mbaud. These
serial baud rates correspond to
8B/10B encoded byte rates of 50
Mbytes/sec and 100 Mbytes/sec
respectively. The proper setting
of a single pin on each chip
selects the desired rate of
operation.
Description
The HDMP-1512 transmitter and
the HDMP-1514 receiver are
bipolar integrated circuits,
separately packaged, in 80 pin M-
Quad packages. They are used to
build a high speed Fibre Channel
link for point to point data com-
munications. Shown in Figure 1 is
a typical full duplex point-to-
point Fibre Channel link. The
sending system provides parallel,
8B/10B, encoded data and a
transmit byte clock to the HDMP-
1512 transmitter. Using the trans-
mit byte clock, the transmitter
Several features, exclusive to this
chip-set, make it ideal for use in
Fibre Channel links. In addition,
the laser driver on the transmitter
chip, the dual loss of light
detectors on the receiver chip,
and the power supervisor and
power reset features make this
chip-set ideal for use with laser
optics. The serial cable driver
(transmitter chip), and the cable
equalizer (on the receiver chip),
can be operated in conjunction
with, or as an alternative to, the
laser driver. The laser driver can
also be driven directly with an
external high speed serial input.
Altogether, the various features,
input/output options, and
flexibility of this chip-set make
several unique link configurations
possible. In particular, it is ideally
suited for use in applications
where conformance to the FCSI
specification # 301-Rev 1.0,
Gbaud Link Module Specification,
is desired.
656
5964-6637E (4/96)

HDMP-1514相關(guān)型號(hào)PDF文件下載

  • 型號(hào)
    版本
    描述
    廠商
    下載
  • 英文版
    Optoelectronic
    ETC
  • 英文版
    Optoelectronic
    ETC
  • 英文版
    FIBER OPTIC SUPPORT CIRCUIT
    ETC
  • 英文版
    FIBER OPTIC SUPPORT CIRCUIT
    ETC
  • 英文版
    FIBER OPTIC SUPPORT CIRCUIT
    ETC
  • 英文版
    1.0625-1.25 GBd Single Port Bypass Circuit wirh CDR for Fibr...
    ETC
  • 英文版
    Port Bypass Circuits for Fibre Channel Arbitrated Loop Stand...
    HP [Agilen...
  • 英文版
    Single Port Bypass Circuit with CDR & Data Valid Detection C...
    HP [Agilen...
  • 英文版
    Quad Port Bypass Circuit for Fibre Channel Arbitrated Loops
    AGILENT
  • 英文版
    Quad Port Bypass Circuit for Fibre Channel Arbitrated Loops
    HP [Agilen...
  • 英文版
    Quad Port Bypass Circuit for Fibre Channel Arbitrated Loops
    AGILENT
  • 英文版
    Quad Port Bypass Circuit for Fibre Channel Arbitrated Loops
    HP [Agilen...
  • 英文版
    Quad Port Bypass Circuit with CDR for Fibre Channel Arbitrat...
    AGILENT
  • 英文版
    Quad Port Bypass Circuit with CDR for Fibre Channel Arbitrat...
    HP [Agilen...
  • 英文版
    Octal Cell Port Bypass Circuit without Clock and Data Recove...
    AGILENT
  • 英文版
    Octal Cell Port Bypass Circuit without Clock and Data Recove...
    HP [Agilen...
  • 英文版
    Octal Cell Port Bypass Circuit with CDR and Data Valid Detec...
    HP [Agilen...
  • 英文版
    AGILENT HDMP-0552 QUAD PORT BYPASS CIRCUIT WITH CDR AND DATA...
    ETC
  • 英文版
    AGILENT HDMP-0552 QUAD PORT BYPASS CIRCUIT WITH CDR A...
    ETC [ETC]
  • 英文版
    Receiver
    ETC

掃碼下載APP，
一鍵連接廣大的電子世界。

在線人工客服

買(mǎi)家服務(wù)：
賣(mài)家服務(wù)：
技術(shù)客服：

0571-85317607

網(wǎng)站技術(shù)支持

13606545031

客服在線時(shí)間周一至周五
9:00-17:30

關(guān)注官方微信號(hào)，
第一時(shí)間獲取資訊。

建議反饋

聯(lián)系人：

聯(lián)系方式：

按住滑塊，拖拽到最右邊
>>
感謝您向阿庫(kù)提出的寶貴意見(jiàn)，您的參與是維庫(kù)提升服務(wù)的動(dòng)力！意見(jiàn)一經(jīng)采納，將有感恩紅包奉上哦！