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HDMP-1034A Datasheet

  • HDMP-1034A

  • 1.4 GBd Receiver Chip with CIMT Encoder/Decoder and Variable...

  • 247.61KB

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Agilent HDMP-1032A/1034A
Transmitter/Receiver
Chip Set
Data Sheet
Features
鈥?3.3 V supply, low power
dissipation
660 mW Tx, 792 mW Rx
鈥?On-chip encode/decode using
Conditional Inversion Master
Transition (CIMT) protocol
鈥?1:N broadcast ready
configurable receiver inputs allow
multi-point data broadcast using a
single transmitter
鈥?Parallel Automatic
Synchronization System (PASS)
allows receiver to read recovered
words with local reference clock
鈥?Robust simplex mode
鈥?Wide range serial rate
260-1400 MBaud (user selectable)
鈥?5 V tolerant TTL interface
16 or 17 Bits wide
鈥?Low cost 64 pin plastic package
14x14 mm
2
PQFP
Applications
鈥?Cellular base station
鈥?ATM switch
鈥?Backplane/bus extender
鈥?Video, image acquisition
鈥?Point to point data link
鈥?Implement SCI-FI standard
1.4 GBd Transmitter/Receiver Chip Set with
CIMT Encoder/Decoder and Variable Data Rate.
Description
The HDMP-1032A transmitter and
HDMP-1034A receiver are used
together to build a high-speed
data link for point-to-point
communication. These silicon
bipolar transmitter and receiver
chips are housed in standard
plastic 64 pin PQFP packages.
From the user鈥檚 viewpoint, these
products can be thought of as a
鈥渧irtual ribbon cable鈥?interface for
the transmission of data and con-
trol words. A parallel word loaded
into the Tx (transmitter) chip is
delivered to the Rx (receiver) chip
over a serial channel and is then
reconstructed into its original par-
allel form. The channel can be ei-
ther a coaxial copper cable or
optical link
The chip set hides from the
user the complexity of encoding,
multiplexing, clock extraction,
demultiplexing and decoding. The
CIMT encoding scheme used en-
sures the DC balance of the serial
line. When data or control words
are not being sent the transmitter
sends idle words.
The serial data rate of the Tx/Rx
link is selectable in three ranges
and extends from 208 to 1120
Mbit/s. This translates into an
encoded serial rate of 260 to
1400 MBaud. The parallel data
interface is 16 bit TTL. A flag bit
is also present and can be used as
an extra 17th bit under the user鈥檚
control. This bit can be used as
an even or odd word indicator
for dual-word transmission. The
encoding of the flag bit can be
scrambled to reduce the probabil-
ity of erroneous word alignment.
A user control space is also
provided. If TXCNTL is asserted
on the Tx chip, the least signifi-
cant 14 bits of the data will be
sent and the RXCNTL line on the
Rx chip will indicate the data is
a Control Word.
At the Rx, the PASS feature
allows the recovered words to
be clocked out with the local

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