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HDMP-1024 Datasheet

  • HDMP-1024

  • Low Cost Gigabit Rate Transmit/Receive Chip Set with TTL I/O...

  • 316.30KB

  • 40頁

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Low Cost Gigabit Rate
Transmit/Receive Chip Set with
TTL I/Os
Preliminary Technical Data
Features
鈥?/div>
Transparent, Extended
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
Ribbon Cable Replacement
Implemented in a Low Cost
Aluminum M-Quad 80
Package
High-Speed Serial Rate
150-1500 MBaud
Standard TTL Interface
16, 17, 20, or 21 Bits Wide
Reliable Monolithic Silicon
Bipolar Implementation
On-Chip Phase-Locked
Loops
- Transmit Clock Generation
- Receive Clock Extraction
data. Parallel data (a frame)
loaded into the Tx (transmitter)
chip is delivered to the Rx
(receiver) chip over a serial
channel, which can be either a
coaxial copper cable or optical
link.
The chip set hides from the user
all the complexity of encoding,
multiplexing, clock extraction,
demultiplexing and decoding.
Unlike other links, the phase-
locked-loop clock extraction
circuit also transparently provides
for frame synchronization鈥搕he
user is not troubled with the
periodic insertion of frame syn-
chronization words. In addition,
the dc balance of the line code is
automatically maintained by the
chip set. Thus, the user can
transmit arbitrary data without
restriction. The Rx chip also
includes a state-machine con-
troller (SMC) that provides a
startup handshake protocol for
the duplex link configuration.
The serial data rate of the T/R link
is selectable in four ranges (see
tables on page 5), and extends
from 120 Mbits/s up to 1.25
Gbits/s. The parallel data interface
is 16 or 20 bit TTL, pin select-
able. A flag bit is available and
can be used as an extra 17th or
21st bit under the user鈥檚 control.
The flag bit can also be used as an
even or odd frame indicator for
dual-frame transmission. If not
HDMP-1022 Transmitter
HDMP-1024 Receiver
used, the link performs expanded
error detection.
The serial link is synchronous,
and both frame synchronization
and bit synchronization are main-
tained. When data is not available
to send, the link maintains
synchronization by transmitting
fill frames. Two (training) fill
frames are reserved for
handshaking during link startup.
User control space is also sup-
ported. If Control Available is
asserted at the Tx chip, the least
significant 14 or 18 bits of the
data are sent and the Rx Control
Available line will indicate the
data as a Control Word.
It is the intention of this data
sheet to provide the design
engineer all of the information
regarding the HDMP-1022/1024
chipset necessary to design this
product into their application. To
assist you in using this data sheet,
the following Table of Contents is
provided.
Applications
鈥?/div>
Backplane/Bus Extender
鈥?/div>
Video, Image Acquisition
鈥?/div>
Point to Point Data Links
鈥?/div>
Implement SCI-FI Standard
鈥?/div>
Implement Serial HIPPI
Specification
Description
The HDMP-1022 transmitter and
the HDMP-1024 receiver are used
to build a high-speed data link for
point-to-point communication.
The monolithic silicon bipolar
transmitter chip and receiver chip
are each provided in a standard
aluminum M-Quad 80 package.
From the user鈥檚 viewpoint, these
products can be thought of as
providing a 鈥渧irtual ribbon cable鈥?/div>
interface for the transmission of
615
(5/97)

HDMP-1024相關型號PDF文件下載

  • 型號
    版本
    描述
    廠商
    下載
  • 英文版
    Optoelectronic
    ETC
  • 英文版
    Optoelectronic
    ETC
  • 英文版
    FIBER OPTIC SUPPORT CIRCUIT
    ETC
  • 英文版
    FIBER OPTIC SUPPORT CIRCUIT
    ETC
  • 英文版
    FIBER OPTIC SUPPORT CIRCUIT
    ETC
  • 英文版
    1.0625-1.25 GBd Single Port Bypass Circuit wirh CDR for Fibr...
    ETC
  • 英文版
    Port Bypass Circuits for Fibre Channel Arbitrated Loop Stand...
    HP [Agilen...
  • 英文版
    Single Port Bypass Circuit with CDR & Data Valid Detection C...
    HP [Agilen...
  • 英文版
    Quad Port Bypass Circuit for Fibre Channel Arbitrated Loops
    AGILENT
  • 英文版
    Quad Port Bypass Circuit for Fibre Channel Arbitrated Loops
    HP [Agilen...
  • 英文版
    Quad Port Bypass Circuit for Fibre Channel Arbitrated Loops
    AGILENT
  • 英文版
    Quad Port Bypass Circuit for Fibre Channel Arbitrated Loops
    HP [Agilen...
  • 英文版
    Quad Port Bypass Circuit with CDR for Fibre Channel Arbitrat...
    AGILENT
  • 英文版
    Quad Port Bypass Circuit with CDR for Fibre Channel Arbitrat...
    HP [Agilen...
  • 英文版
    Octal Cell Port Bypass Circuit without Clock and Data Recove...
    AGILENT
  • 英文版
    Octal Cell Port Bypass Circuit without Clock and Data Recove...
    HP [Agilen...
  • 英文版
    Octal Cell Port Bypass Circuit with CDR and Data Valid Detec...
    HP [Agilen...
  • 英文版
    AGILENT HDMP-0552 QUAD PORT BYPASS CIRCUIT WITH CDR AND DATA...
    ETC
  • 英文版
    AGILENT HDMP-0552 QUAD PORT BYPASS CIRCUIT WITH CDR A...
    ETC [ETC]
  • 英文版
    Receiver
    ETC

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