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HDMP-0552 Datasheet

  • HDMP-0552

  • AGILENT HDMP-0552 QUAD PORT BYPASS CIRCUIT WITH CDR AND DATA...

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Agilent HDMP-0552 Quad Port Bypass
Circuit with CDR and Data Valid
Detection
For Fibre Channel Arbitrated Loops
Data Sheet
Features
鈥?Supports 1.0625/2.125 GBd Fibre
Channel operation
鈥?Quad PBC/CDR in one package
鈥?CDR location determined by
choice of cable input/output
鈥?Amplitude valid detection on
FM_NODE[0] input
鈥?Data valid detection on
FM_NODE[0] input
鈥?/div>
Run length violation detection
鈥?/div>
Comma detection
鈥?Configurable for both single-
frame and multi-frame
detection
鈥?Speed select pin for 1 or 2 GBd
operation
鈥?Single REFCLK for 1 or 2 GBd
operation
鈥?CDR selectable via external pin
鈥?Enable/disable equalizers on all
inputs
鈥?Enable/disable selected high-
speed output drivers
鈥?High speed LVPECL I/O
鈥?Buffered line logic (BLL) outputs
(no external bias resistors
required)
鈥?1.1 W typical power at V
CC
= 3.3 V
鈥?Advanced 0.35 碌 BiCMOS
technology
鈥?64 Pin, 10 mm, low cost plastic
QFP package
Applications
鈥?RAID, JBOD, BTS cabinets
鈥?1=> 1-4 serial buffer with or
without CDR
Description
The HDMP-0552 is a Quad Port
Bypass Circuit (PBC) with Clock
and Data Recovery (CDR) and
data valid detection capability
included. See Figure 1 for block
diagram. This device minimizes
part count, cost and jitter
accumulation while repeating
incoming signals. Port Bypass
Circuits are used in hard disk
arrays constructed in Fibre
Channel Arbitrated Loop (FC-AL)
configurations. By using Port
Bypass Circuits, hard disks may
be pulled out or swapped while
other disks in the array are
available to the system.
A PBC consists of multiple 2:1
multiplexers daisy chained along
with a CDR. Each port has two
modes of operation: 鈥渄isk in
loop鈥?and 鈥渄isk bypassed.鈥?When
the 鈥渄isk in loop鈥?mode is
selected, the loop goes into and
out of the disk drive at that port.
For example, data goes from the
HDMP-0552鈥檚 TO_NODE[n]鹵
differential output pins to the
Disk Drive Transceiver IC (for
example, an HDMP-263x) Rx鹵
differential input pins. Data from
the Disk Drive Transceiver IC
Tx鹵 differential output pins goes
to HDMP-0552鈥檚 FM_NODE[n]鹵
differential input pins. Figure 2
and Figure 3 show connection
diagrams for disk drive array
applications. When the 鈥渄isk
bypassed鈥?mode is selected, the
disk drive is either absent or
nonfunctional, and the loop
bypasses the hard disk.
Multiple HDMP-0552鈥檚 may be
cascaded or connected to other
members of the HDMP-04xx
family through the FM_LOOP and
TO_LOOP pins to create loops for
arrays of disk drives greater than
4. See Table 3 to identify which
of the 5 cells (0:4) provides
FM_LOOP, TO_LOOP pins (cell
connected to cable).
CAUTION: As with all semiconductor ICs, it is advised that normal static precautions be taken in the handling and assembly of
this component to prevent damage and/or degradation which may be induced by electrostatic discharge (ESD).

HDMP-0552相關(guān)型號PDF文件下載

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  • 英文版
    Receiver
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