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HDMP-0452 Datasheet

  • HDMP-0452

  • Quad Port Bypass Circuit with CDR for Fibre Channel Arbitrat...

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Agilent HDMP-0452
Quad Port Bypass Circuit
with CDR for Fibre Channel
Arbitrated Loops
Data Sheet
Description
The HDMP-0452 is a Quad Port
Bypass Circuit (PBC) with a Clock
and Data Recovery (CDR) circuit
included. This device minimizes
part count, cost and jitter accumula-
tion while repeating incoming sig-
nals. Port Bypass Circuits are used
in hard disk arrays constructed in
Fibre Channel Arbitrated Loop
(FC-AL) configurations. By using
Port Bypass Circuits, hard disks
may be pulled out or swapped while
other disks in the array are available
to the system.
A Port Bypass Circuit (PBC) con-
sists of multiple 2:1 multiplexers
daisy chained along with a CDR.
Each port has two modes of opera-
tion: 鈥渄isk in loop鈥?and 鈥渄isk by-
passed鈥? When the 鈥渄isk in loop鈥?/div>
mode is selected, the loop goes into
and out of the disk drive at that
port. For example, data goes from
the HDMP-0452鈥檚 TO_NODE[n]鹵
differential output pins to the Disk
Drive Transceiver IC鈥檚 (e.g., an
HDMP-1536A) Rx鹵 differential
input pins. Data from the Disk Drive
Transceiver IC鈥檚 Tx鹵 differential
outputs goes to the HDMP-0452鈥檚
FM_NODE[n]鹵 differential input
pins. Figures 3 and 4 show con-
nection diagrams for disk drive
array applications. When the 鈥渄isk
bypassed鈥?mode is selected, the
disk drive is either absent or non-
functional and the loop bypasses
the hard disk.
The 鈥渄isk bypassed鈥?mode is
enabled by pulling the
BYPASS[n]鈥?pin low. Leave
BYPASS[n]鈥?floating to enable
the 鈥渄isk in loop鈥?mode. HDMP-
0452s may be cascaded with other
members of the HDMP-04XX/
HDMP-05XX family through the
FM_LOOP and TO_LOOP pins to
accommodate any number of hard
disks. See Table 2 to identify
which of the 5 cells (0:4) will
provide FM_LOOP and TO_LOOP
pins (cable connections). The
unused cells in this PBC may be
bypassed by using pulldown
resistors on the BYPASS[n]鈥?pins
for these cells.
Features
鈥?Supports 1.0625 GBd fibre
channel operation
鈥?Supports 1.25 GBd Gigabit
Ethernet (GE) operation
鈥?Quad PBC/CDR in one package
鈥?CDR location determined by
choice of cable input/output
鈥?Valid amplitude detection on
FM_NODE[0] input
鈥?Equalizers on all inputs
鈥?High speed LVPECL I/O
鈥?Buffered Line Logic (BLL) outputs
(no external bias resistors
required)
鈥?0.66 W typical power at
V
CC
= 3.3 V
鈥?44 pin, 10 mm, low cost plastic
QFP package
Applications
鈥?RAID, JBOD, BTS cabinets
鈥?1 => 1-4 serial buffer with or
w/o CDR
HDMP-0452
CAUTION: As with all semiconductor ICs, it is advised that normal static precautions be taken in the handling and assem-
bly of this component to prevent damage and/or degradation which may be induced by Electrostatic Discharge (ESD).

HDMP-0452相關(guān)型號(hào)PDF文件下載

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