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HD74SSTV16858 Datasheet

  • HD74SSTV16858

  • Datasheet|ADE-205-351B|JUN.20.01|80K

  • 82.23KB

  • 13頁

  • ETC

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HD74SSTV16858
1:2 11-bit SSTL_2 Registered Buffer
ADE-205-351B (Z)
Rev.2
June 2001
Description
The HD74SSTV16858 is a 1:2 11-bit registered buffer designed for 2.3 V to 2.7 V Vcc operation and
LVCMOS reset (RESET) input / SSTL_2 data (D) inputs and CLK input.
Data flow from D to QA, QB is controlled by differential clock pins (CLK,
CLK)
and the
RESET.
Data is
triggered on the positive edge of the positive clock (CLK), and the negative clock (CLK) must be used to
maintain noise margins. When
RESET
is low, all registers are reset and all outputs are low.
To ensure defined outputs from the register before a stable clock has been supplied,
RESET
must be held in
the low state during power up.
Features
鈥?/div>
Supports LVCMOS reset (RESET) input / SSTL_2 data (D) inputs and CLK input
鈥?/div>
Differential SSTL_2 (Stub series terminated logic) CLK signal
鈥?/div>
Flow through architecture optimizes PCB layout
Function Table
Inputs
RESET
L
H
H
H
H:
L:
X:
鈫?/div>
:
鈫?
Note:
CLK
X
鈫?/div>
鈫?/div>
L or H
CLK
X
鈫?/div>
鈫?/div>
H or L
D
X
H
L
X
Outputs
QA
L
H
L
Q
0
*1
QB
L
H
L
Q
0
*1
High level
Low level
Immaterial
Low to high transition
High to low transition
1. Output level before the indicated steady state input conditions were established.

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