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HD74LVC374AFPEL Datasheet

  • HD74LVC374AFPEL

  • Octal D-type Flip Flops with 3-state Outputs

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HD74LVC374A
Octal D-type Flip Flops with 3-state Outputs
REJ03D0355鈥?400Z
(Previous ADE-205-113B (Z))
Rev.4.00
Jul. 27, 2004
Description
The HD74 LVC374A has eight edge trigger D type flip flops with three state outputs in a 20 pin package. Data at the
D inputs meeting set up requirements are transferred to the Q outputs on positive going transitions of the clock input.
When the clock input goes low, data at the D inputs will be retained at the outputs until clock input returns high again.
When a high logic level is applied to the output control input, all outputs go to a high impedance state, regardless of
what signals are present at the other inputs and the state of the storage elements. Low voltage and high-speed operation
is suitable at the battery drive product (note type personal computer) and low power consumption extends the life of a
battery for long time operation.
Features
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
V
CC
= 2.0 V to 5.5 V
All inputs V
IH
(Max.) = 5.5 V (@V
CC
= 0 V to 5.5 V)
All outputs V
OUT
(Max.) = 5.5 V (@V
CC
= 0 V or output off state)
Typical V
OL
ground bounce < 0.8 V (@V
CC
= 3.3 V, Ta = 25 擄C)
Typical V
OH
undershoot > 2.0 V (@V
CC
= 3.3 V, Ta = 25擄C)
High output current 鹵24 mA (@V
CC
= 3.0 V to 5.5 V)
Ordering Information
Package Type
SOP鈥?0 pin (JEITA)
TSSOP鈥?0 pin
Package Code
FP鈥?0DAV
TTP鈥?0DAV
Package
Abbreviation
FP
T
Taping Abbreviation
(Quantity)
EL (2,000 pcs/reel)
ELL (2,000 pcs/reel)
Part Name
HD74LVC374AFPEL
HD74LVC374ATELL
Note: Please consult the sales office for the above package availability.
Function Table
Inputs
G
H
L
L
L
H:
L:
X:
Z:
鈫?/div>
:
Q
0
:
CK
X
鈫?/div>
鈫?/div>
L
D
X
L
H
X
Output Q
Z
L
H
Q
0
High level
Low level
Immaterial
High impedance
Low to high transition
Level of Q before the indicated steady input conditions were established.
Rev.4.00 Jul. 27, 2004 page 1 of 7

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