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HD74LVC16373ATEL Datasheet

  • HD74LVC16373ATEL

  • 16-bit D-type Transparent Latches with 3-state Outputs

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HD74LVC16373A
16-bit D-type Transparent Latches with 3-state Outputs
REJ03D0366鈥?400Z
(Previous ADE-205-121B (Z))
Rev.4.00
Jul. 29, 2004
Description
The HD74LVC16373A has sixteen D type latches with three state outputs in a 48 pin package. When the latch enable
input is high, the Q outputs will follow the D inputs. When the latch enable goes low, data at the D inputs will be
retained at the outputs until latch enable returns high again. When a high logic level is applied to the output control
input (1G, 2G), all outputs go to a high impedance state, regardless of what signals are present at the other inputs and
the state of the storage elements. Low voltage and high-speed operation is suitable at the battery drive product (note
type personal computer) and low power consumption extends the life of a battery for long time operation.
Features
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
V
CC
= 2.0 V to 5.5 V
All inputs V
IH
(Max.) = 5.5 V (@V
CC
= 0 V to 5.5 V)
All outputs V
OUT
(Max.) = 5.5 V (@V
CC
= 0 V or output off state)
Typical V
OL
ground bounce < 0.8 V (@V
CC
= 3.3 V, Ta = 25擄C)
Typical V
OH
undershoot > 2.0 V (@V
CC
= 3.3 V, Ta = 25擄C)
High output current 鹵24 mA (@V
CC
= 3.0 V to 5.5 V)
Ordering Information
Package Type
TSSOP鈥?8 pin
Package Code
TTP鈥?8DBV
Package
Abbreviation
T
Taping Abbreviation
(Quantity)
EL (1,000 pcs/reel)
Part Name
HD74LVC16373ATEL
Function Table
Inputs
G
H
L
L
L
H:
L:
X:
Z:
Q
0
:
LE
X
H
H
L
D
X
L
H
X
Output Q
Z
L
H
Q
0
High level
Low level
Immaterial
High impedance
Level of Q before the indicated steady input conditions were established.
Rev.4.00 Jul. 29, 2004 page 1 of 9

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