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HD74LV2G126AUSE Datasheet

  • HD74LV2G126AUSE

  • Dual Bus Buffer with 3?state Output

  • 10頁(yè)

  • RENESAS

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HD74LV2G126A
Dual Bus Buffer with 3鈥搒tate Output
REJ03D0100鈥?500Z
(Previous ADE-205-348D (Z))
Rev.5.00
Sep.30.2003
Description
The HD74LV2G126A has dual bus buffer with 3鈥搒tate output in a 8 pin package. Output is disabled when
the associated output enable (OE) input is low. To ensure the high impedance state during power up or
power down, OE should be connected to V
CC
through a pull-down resistor; the minimum value of the
resistor is determined by the current souring capability of the driver. Low voltage and high-speed operation
is suitable for the battery powered products (e.g., notebook computers), and the low power consumption
extends the battery life.
Features
鈥?/div>
The basic gate function is lined up as Renesas uni logic series.
鈥?/div>
Supplied on emboss taping for high-speed automatic mounting.
鈥?/div>
Electrical characteristics equivalent to the HD74LV126A
Supply voltage range : 1.65 to 5.5 V
Operating temperature range : 鈥?0 to +85擄C
鈥?/div>
All inputs V
IH
(Max.) = 5.5 V (@V
CC
= 0 V to 5.5 V)
All outputs V
O
(Max.) = 5.5 V (@V
CC
= 0 V, Output : Z)
鈥?/div>
Output current 鹵6 mA (@V
CC
= 3.0 V to 3.6 V), 鹵12 mA (@V
CC
= 4.5 V to 5.5 V)
鈥?/div>
All the logical input has hysteresis voltage for the slow transition.
鈥?/div>
Ordering Information
Part Name
Package Type
Package Code
TTP-8DBV
Package
Abbreviation
US
Taping Abbreviation
(Quantity)
E (3,000 pcs/reel)
HD74LV2G126AUSE SSOP-8 pin
Rev.5.00, Sep.30.2003, page 1 of 9

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