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HD74LV175AFP Datasheet

  • HD74LV175AFP

  • FLIP-FLOP|QUAD|D TYPE|LV-CMOS|SOP|16PIN|PLASTIC

  • 66.17KB

  • 15頁

  • ETC

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HD74LV175A
Quad. D-type Flip-Flops with Clear
ADE-205-270 (Z)
1st Edition
April 1999
Description
Information at the D inputs of the HD74LV175A is transferred to the Q and
Q
outputs on the positive going
edge of the clock pulse. Both true and complement outputs from each flip-flop are externally available.
All four flip-flops are controlled by a common clock and common clear. Clearing is accomplished by a
negative pulse at the clear input. All four Q outputs are cleared to a logic low level and all four
Q
outputs
to a logic high level. Low-voltage and high-speed operation is suitable for battery-powered products (e.g.,
notebook computers), and the low-power consumption extends the battery life.
Features
鈥?/div>
V
CC
= 2.0 V to 5.5 V operation
鈥?/div>
All inputs V
IH
(Max.) = 5.5 V (@V
CC
= 0 V to 5.5 V)
鈥?/div>
All outputs V
O
(Max.) = 5.5 V (@V
CC
= 0 V)
鈥?/div>
Typical V
OL
ground bounce < 0.8 V (@V
CC
= 3.3 V, Ta = 25擄C)
鈥?/div>
Typical V
OH
undershoot > 2.3 V (@V
CC
= 3.3 V, Ta = 25擄C)
鈥?/div>
Output current
鹵6
mA (@V
CC
= 3.0 V to 3.6 V),
鹵12
mA (@V
CC
= 4.5 V to 5.5 V)
Function Table
Inputs
CLR
L
H
H
H
Note: H:
L:
X:
鈫?
鈫?
CLK
X
鈫?/div>
鈫?/div>
鈫?/div>
High level
Low level
Immaterial
Low to high transition
High to low transition
D
X
H
L
X
Outputs
Q
L
H
L
no change
Q
H
L
H
no change

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