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HD74LV138A Datasheet

  • HD74LV138A

  • Hitachi Semiconductor [3-to-8 line Decoder / Demultiplexers...

  • HITACHI

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HD74LV138A
3-to-8 line Decoder / Demultiplexers
ADE-205-261 (Z)
1st Edition
March 1999
Description
The HD74LV138A is designed to be used in high-performance memory-decoding or data-routing
applications requiring very short propagation delay times. The conditions at the binary-select inputs and
the three enable inputs select one of eight input lines.
Two active-low and one active-high enable inputs reduce the need for external gates or inverters when
expanding. A 24-line decoder can be implemented without external inverters and a 32-line decoder
requires only one inverter.
An enable input can be used as a data input for demultiplexing applications.
Low-voltage and high-speed operation is suitable for the battery-powered products (e.g., notebook
computers), and the low-power consumption extends the battery life.
Features
鈥?/div>
V
CC
= 2.0 V to 5.5 V operation
鈥?/div>
All inputs V
IH
(Max.) = 5.5 V (@V
CC
= 0 V to 5.5 V)
鈥?/div>
All outputs V
O
(Max.) = 5.5 V (@V
CC
= 0 V)
鈥?/div>
Typical V
OL
ground bounce < 0.8 V (@V
CC
= 3.3 V, Ta = 25擄C)
鈥?/div>
Typical V
OH
undershoot > 2.3 V (@V
CC
= 3.3 V, Ta = 25擄C)
鈥?/div>
Output current
鹵6
mA (@V
CC
= 3.0 V to 3.6 V),
鹵12
mA (@V
CC
= 4.5 V to 5.5 V)

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