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HD74LV126ATELL Datasheet

  • HD74LV126ATELL

  • Quad. Bus Buffer Gates with 3-state Outputs

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HD74LV126A
Quad. Bus Buffer Gates with 3-state Outputs
REJ03D0316鈥?300Z
(Previous ADE-205-259A (Z))
Rev.3.00
Jun. 03, 2004
Description
The HD74LV126A features independent line drivers with three state outputs. Each output is disabled when the
associated output enable (OE) input is low. To ensure the high impedance state during power up or power down, OE
should be connected to GND through a pull-down resistor; the minimum value of the resistor is determined by the
current souring capability of the driver. Low-voltage and high-speed operation is suitable for the battery-powered
products (e.g., notebook computers), and the low-power consumption extends the battery life.
Features
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
V
CC
= 2.0 V to 5.5 V operation
All inputs V
IH
(Max.) = 5.5 V (@V
CC
= 0 V to 5.5 V)
All outputs V
O
(Max.) = 5.5 V (@V
CC
= 0 V)
Typical V
OL
ground bounce < 0.8 V (@V
CC
= 3.3 V, Ta = 25擄C)
Typical V
OH
undershoot > 2.3 V (@V
CC
= 3.3 V, Ta = 25擄C)
Output current 鹵8 mA (@V
CC
= 3.0 V to 3.6 V), 鹵16 mA (@V
CC
= 4.5 V to 5.5 V)
Ordering Information
Package Type
SOP鈥?4 pin(JEITA)
SOP鈥?4 pin(JEDEC)
TSSOP鈥?4 pin
Package Code
FP鈥?4DAV
FP鈥?4DNV
TTP鈥?4DV
Package
Abbreviation
FP
RP
T
Taping Abbreviation
(Quantity)
EL (2,000 pcs/reel)
EL (2,500 pcs/reel)
ELL (2,000 pcs/reel)
Part Name
HD74LV126AFPEL
HD74LV126ARPEL
HD74LV126ATELL
Note: Please consult the sales office for the above package availability.
Function Table
Inputs
OE
H
H
L
Note: H:
L:
X:
Z:
High level
Low level
Immaterial
High impedance
A
H
L
X
Output Y
H
L
Z
Rev.3.00 Jun. 03, 2004 page 1 of 9

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