HD74HCT623FP Datasheet

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HD74HCT620/HD74HCT623

Octal Bus Transceivers (with inverted 3-state outputs)/

Octal Bus Transceivers (with 3-state outputs)

Description

This octal transceiver is designed for asynchronous two-way communication between data buses. The

control function implementation allows for maximum flexibility in timng.

This device allows data transmission from A bus to the B bus or from the B bus to the A bus depending

upon the logic levels at the enable inputs (GBA and GAB).

The enable inputs can be used to disable the device so that the buses are affectively isolated.

The dual-enable configuration gives these devices the capability to store data by simultaneous enabling of

GBA

and GAB. Each output reinforces its input in this transceiver configuration. Thus, when both control

inputs are enabled and all other data sources to the two sets of bus lines are at high impedance, both sets of

bus lines (16 in all) will remain at their last states. The 8-bit codes appearing on the two sets of buses will

be identical for the HD74HCT623 or complementary for the HD74HCT620.

Features

鈥?/div>

LSTTL Output Logic Level Compatibility as well as CMOS Output Compatibility

High Speed Operation: t

(Bus to Bus) = 15 ns typ (C

= 50 pF)

High Output Current: Fanout of 15 LSTTL Loads

Wide Operating Voltage: V

= 4.5 to 5.5 V

Low Input Current: 1 碌A(chǔ) max

Low Quiescent Supply Current: I

(static) = 4 碌A(chǔ) max (Ta = 25擄C)

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