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HD74HCT563 Datasheet

  • HD74HCT563

  • Octal Transparent Latches (with 3-state outputs)

  • 11頁

  • HITACHI

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HD74HCT563/HD74HCT573
Octal Transparent Latches (with 3-state outputs)
Description
When the latch enable (LE) input is high, the Q outputs of HD74HCT563 will follow the inversion of the D
inputs and the Q outputs of HD74HCT573 will follow the D inputs.
When the latch enable goes low, data at the D inputs will be retained at the outputs until latch enabled
returns high again. When a high logic level is applied to the output control input, all outputs go to a high
impedance state, regardless of what signals are present at the other inputs and the state of the storage
elements.
Features
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LSTTL Output Logic Level Compatibility as well as CMOS Output Compatibility
High Speed Operation: t
pd
(D to Q,
Q)
= 13 ns typ (C
L
= 50 pF)
High Output Current: Fanout of 15 LSTTL Loads
Wide Operating Voltage: V
CC
= 4.5 to 5.5 V
Low Input Current: 1 碌A(chǔ) max
Low Quiescent Supply Current: I
CC
(static) = 4 碌A(chǔ) max (Ta = 25擄C)
Function Table
Outputs
Output Control
L
L
L
H
Latch Enable
H
H
L
X
Data
H
L
X
X
HD74HCT563
L
H
Q
0
Z
HD74HCT573
H
L
Q
0
Z

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