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HD74HCT237RP Datasheet

  • HD74HCT237RP

  • DECODER/DEMUX|3-TO-8-LINE|HCT-CMOS|SOP|16PIN|PLASTIC

  • 58.74KB

  • 8頁

  • ETC

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HD74HCT237
3-to-8-line Decoder/Demultiplexer with Address Latch
Description
The HD74HCT237 decodes a three-bit Address to one-of-eight active-high outputs. The device has a
transparent latch for storage of the Address. Two Chip Selects, one active-low and one active-high, are
provided to facilitate the demultiplexing, cascading, and chip-selecting functions.
The demultiplexing function is accomplished by using the Address inputs to select the desired device
output, and then by using one of the Chip Select as a data input while holding the other one active.
The HD74HCT237 is the noninverting version of the HD74HCT137.
Features
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LSTTL Output Logic Level Compatibility as well as CMOS Output Compatibility
High Speed Operation: t
pd
(A, B, C to Y) = 23 ns typ (C
L
= 50 pF)
High Output Current: Fanout of 10 LSTTL Loads
Wide Operating Voltage: V
CC
= 4.5 to 5.5 V
Low Input Current: 1 碌A(chǔ) max
Low Quiescent Supply Current: I
CC
(static) = 4 碌A(chǔ) max (Ta = 25擄C)

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