HD74HC670 Datasheet

閱覽下載糾錯(cuò) 0

掃碼查看芯片數(shù)據(jù)手冊(cè)

上傳產(chǎn)品規(guī)格書

HD74HC670

4-by-4 Register File (with 3-state outputs)

Description

The HD74HC670, 16-bit register file is organized as 4 words of 4 bits each and separate on-chip decoding

is provided for addressing the four word locations to either write-in or retrieve data.

This permits simultaneous writing into one location and reading from another word location. Four data

inputs are available which are used to supply the 4-bit word to be stored. Location of the word is

determined by the write-address inputs A and B in conjunction with a write-enable signal. Data applied at

the inputs should be in its true form. That is, if a high-level signal is desired from the output, a high-level is

applied at the data input for that particular bit location. The latch inputs are arranged so that new data will

be accepted only if both internal address gate inputs are high. When this condition exists, data at the D

input is transferred to the latch output. When the write-enable input, (G

) is high, the data inputs are

inhibited and their levels can cuase no change in the information stored in the internal latches. When the

read-enable input, (G

) is high, the data outputs are inhibited and go into the high-impedance state. The

individual address lines permit direct acquisition of data stored in any four of the latches. Four individual

decoding gates are used to complete the address for reading a word. when the read address is made in

conjunction with the read-enable signal, the word appears at the four outputs.

Features

鈥?/div>

High Speed Operation: t

(Read Select to Q) = 21 ns typ (C

= 50 pF)

High Output Current: Fanout of 15 LSTTL Loads

Wide Operating Voltage: V

= 2 to 6 V

Low Input Current: 1 碌A(chǔ) max

Low Quiescent Supply Current: I

(static) = 4 碌A(chǔ) max (Ta = 25擄C)

建議反饋