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HD74HC563/HD74HC573 Datasheet

  • HD74HC563/HD74HC573

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HD74HC563/HD74HC573
Octal Transparent Latches (with 3-state outputs)
ADE-205-509 (Z)
1st. Edition
Sep. 2000
Description
When the latch enable (LE) input is high, the Q outputs of HD74HC563 will follow the inversion of the D
inputs and the Q outputs of HD74HC573 will follow the D inputs. When the latch enable goes low, data at
the D inputs will be retained at the outputs until latch enable returns high again. When a high logic level is
applied to the output control input, all outputs go to a high impedance state, regardless of what signals are
present at the other inputs and the state of the storage elements.
Features
鈥?/div>
High Speed Operation: t
pd
(Data to Q,
Q)
= 11 ns typ (C
L
= 50 pF)
鈥?/div>
High Output Current: Fanout of 15 LSTTL Loads
鈥?/div>
Wide Operating Voltage: V
CC
= 2 to 6 V
鈥?/div>
Low Input Current: 1 碌A(chǔ) max
鈥?/div>
Low Quiescent Supply Current: I
CC
(static) = 4 碌A(chǔ) max (Ta = 25擄C)
Function Table
Outputs
Output Control
L
L
L
H
Q
0
:
Q
0
:
Latch Enable
H
H
L
X
Data
H
L
X
X
HD74HC563
L
H
Q
0
Z
HD74HD573
H
L
Q
0
Z
level of Q before the indicated Steady-sate input conditions were established.
complement of Q
0
or level of
Q
before the indicated Steady-state input conditions were established.

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