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HD74HC195 Datasheet

  • HD74HC195

  • 4-bit Parallel-Access Shift Register

  • 9頁(yè)

  • HITACHI

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HD74HC195
4-bit Parallel-Access Shift Register
Description
This shift register features parallel inputs, parallel outputs, J-K serial inputs, Shift/Load control input, and a
direct overriding clear. This shift register can operate in two modes: Parallel load; shift from Q
A
towards
Q
D
.
Paralle loading is accomplished by applying the four bits of data, and taking the Shift/Load control Input
low. The data is loaded into the associated flip-flops and appears at the outputs after the positive transition
of the clock input. During parallel loading, serial data flow is inhibited. Serial shifting occurs
synchronously when the Shift/Load control input is high. Serial data for this mode is entered at the J-K
inputs. These inputs allow the first stage to perform as a J-K or toggle flip-flop as shown in the function
table.
Features
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High Speed Operation: t
pd
(Clock to Q) = 13 ns typ (C
L
= 50 pF)
High Output Current: Fanout of 10 LSTTL Loads
Wide Operating Voltage: V
CC
= 2 to 6 V
Low Input Current: 1 碌A(chǔ) max
Low Quiescent Supply Current: I
CC
(static) = 4 碌A(chǔ) max (Ta = 25擄C)

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